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5011 Commits

Author SHA1 Message Date
tangxifan a90740c3b1
Merge pull request #550 from lnis-uofu/dependabot/submodules/yosys-plugins-57a3b87 
Bump yosys-plugins from `770b917` to `57a3b87`
 2022-02-22 11:06:16 -08:00
dependabot[bot] 4904634c32
Bump yosys-plugins from `770b917` to `57a3b87` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `770b917` to `57a3b87`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](770b917aac...57a3b87b7b)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-22 07:26:45 +00:00
tangxifan 2061b2689b
Merge pull request #546 from lnis-uofu/dependabot/submodules/yosys-plugins-770b917 
Bump yosys-plugins from `0fa6d61` to `770b917`
 2022-02-21 16:40:42 -08:00
tangxifan 93e1a79e31
Merge pull request #548 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-21 16:40:21 -08:00
github-actions[bot] f327629bbb Updated Patch Count 2022-02-22 00:02:03 +00:00
tangxifan d4ed003428
Merge pull request #547 from lnis-uofu/release 
[CI] Update patch updater due to release v1.1.0
 2022-02-20 23:34:05 -08:00
tangxifan 8ff68315ab [CI] Update patch updater due to release v1.1.0 2022-02-20 23:32:11 -08:00
dependabot[bot] 9d10153947
Bump yosys-plugins from `0fa6d61` to `770b917` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `0fa6d61` to `770b917`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](0fa6d614fe...770b917aac)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-02-21 07:29:16 +00:00
tangxifan 781ea3f75b
Merge pull request #544 from lnis-uofu/release 
[Version] Bump up for release v1.1
 2022-02-20 21:50:17 -08:00
tangxifan 255993ab1b [Version] Bump up for release v1.1 2022-02-20 20:48:51 -08:00
tangxifan fb513cee41
Merge pull request #543 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-20 16:21:10 -08:00
github-actions[bot] 0a849373d1 Updated Patch Count 2022-02-21 00:02:22 +00:00
tangxifan f430427669
Merge pull request #542 from lnis-uofu/bus_support 
More tests on Bus support: Validate its correctness on Input buses
 2022-02-20 11:37:48 -08:00
tangxifan e33ba667e4 [Test] Add missing file 2022-02-20 10:59:44 -08:00
tangxifan f30de1085c [Test] Cover all the related testcase about bus group 2022-02-19 23:33:16 -08:00
tangxifan b4202f52b4 [Test] debugging 2022-02-19 23:26:29 -08:00
tangxifan 785bb1633d [Test] trying to see if we support busgroup per benchmark in task configuration file 2022-02-19 23:23:36 -08:00
tangxifan cfd4b6f2bf
Merge pull request #541 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2022-02-19 16:38:44 -08:00
github-actions[bot] 4ca45791a4 Updated Patch Count 2022-02-20 00:02:56 +00:00
tangxifan 756c340232
Merge pull request #540 from lnis-uofu/bus_support 
Bus support now support big-endian and little-endian
 2022-02-19 10:23:27 -08:00
tangxifan 1c18d14ad5 [FPGA-Verilog] Add big/little endian support to output ports 2022-02-19 09:23:48 -08:00
tangxifan 3e43a60fdc [FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks 2022-02-19 09:15:38 -08:00
tangxifan 7645d5332d [Test] Update bug group examples on the big endian support 2022-02-18 23:09:03 -08:00
tangxifan b78e58d9bf [Doc] Update doc about big endian syntax in bus group file format 2022-02-18 23:07:18 -08:00
tangxifan 671188dfa4 [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00
tangxifan feaaeea787
Merge pull request #539 from lnis-uofu/bus_support 
Support buses in Verilog testbenches
 2022-02-18 16:48:52 -08:00
tangxifan a78d091606
Merge branch 'master' into bus_support 2022-02-18 15:51:03 -08:00
tangxifan 8116141210 [Doc] Update documentation on the bus group feature 2022-02-18 15:46:25 -08:00
tangxifan 68644ea0f6 [Test] Add the new test to basic regression tests 2022-02-18 15:44:07 -08:00
tangxifan f0ce1e79a3 [Test] Added a new test to validate bus group in full testbench 2022-02-18 15:43:21 -08:00
tangxifan 790715f46a [FPGA-Verilog] Fixing bugs when using bus group in full testbench generator 2022-02-18 15:41:35 -08:00
tangxifan fe9e0ff977 [Test] Add the new test to basic regression tests 2022-02-18 15:38:53 -08:00
tangxifan c897a64ad5 [Script] Add a new example script to test full testbenches using bus group features 2022-02-18 15:37:42 -08:00
tangxifan 223575cf3e [Test] Added a new test for bus group on full testbenches 2022-02-18 15:33:29 -08:00
tangxifan 85c893c94c [Test] Add new test to basic regression tests 2022-02-18 15:30:08 -08:00
tangxifan 5ab84e1861 [Test] Add a new test for bus group 2022-02-18 15:29:33 -08:00
tangxifan b4d59fdd1e [Test] Update bus group file due to little and big endian conversion during yosys/vpr 2022-02-18 15:02:08 -08:00
tangxifan 36543f7f2f [Script] Support simplified rewriting for Yosys on output verilog 2022-02-18 14:54:39 -08:00
tangxifan 401f673f16 [FPGA-Verilog] Streamline codes by using APIs 2022-02-18 14:47:36 -08:00
tangxifan c16ea8d082 [FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches 2022-02-18 14:34:32 -08:00
tangxifan a4dc86a33d [FPGA-Verilog] Now output atom block name removal has a dedicated function 2022-02-18 14:30:46 -08:00
tangxifan f5dd89bbd9 [FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used 2022-02-18 14:08:03 -08:00
tangxifan 8ba3d06392 [Test] Fixed bugs in simulation settings 2022-02-18 12:36:22 -08:00
tangxifan 94fea84a40 [Lib] Fix a bug in memory allocation 2022-02-18 12:36:03 -08:00
tangxifan a4d5172b7c [Test] Fixed bugs that causes VPR failed 2022-02-18 12:31:29 -08:00
tangxifan 43d852d8a1 [Test] Add the bus group test case to basic regression tests 2022-02-18 12:27:25 -08:00
tangxifan 7176037bc4 [Test] Added a new test about bus group 2022-02-18 12:26:00 -08:00
tangxifan 73e6ee964d [Script] Add a new example script showing how to use bus group features 2022-02-18 12:25:34 -08:00
tangxifan 0d620888ab [FPGA-Verilog] Now instance can output bus ports with all the pins 2022-02-18 12:03:26 -08:00
tangxifan aa375fd7a4 [FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator 2022-02-18 11:31:11 -08:00