AurelienUoU
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df873903f8
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Bug fix for non fracturable LUT
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2019-08-14 09:32:15 -06:00 |
Baudouin Chauviere
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69014704ef
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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Baudouin Chauviere
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f140e08093
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Pre-Merge modifications
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2019-07-12 10:48:43 -06:00 |
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Baudouin Chauviere
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a0f1f8d163
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Fix when explicit verilog is NOT used
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2019-07-12 10:39:31 -06:00 |
tangxifan
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f0ecc51b51
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bug fixing to resolve the conflicts between explicit port map and standard cell map
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2019-07-12 10:38:20 -06:00 |
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Baudouin Chauviere
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1431ee2f82
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Fix Explicit verilog
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2019-07-11 22:09:34 -06:00 |
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Baudouin Chauviere
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25f5bc7792
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Latest version, not stable yet but close
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2019-07-09 08:34:01 -06:00 |
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Baudouin Chauviere
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ae05c553d5
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Top module done
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2019-07-08 09:48:33 -06:00 |
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Baudouin Chauviere
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b08513d902
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Big chunk added on the routing part of the explicit mapping
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2019-07-02 14:12:42 -06:00 |
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Baudouin Chauviere
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0e04b88c8f
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Include new files in the parameter spreading
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2019-07-01 11:27:48 -06:00 |
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tangxifan
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711e369fe7
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fixing bugs in the SDC generator and report_timing
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2019-06-26 18:09:09 -06:00 |
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tangxifan
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4d2a3680be
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support bus explicit port mapping to standard cells (for BRAMs)
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2019-06-14 11:09:15 -06:00 |
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tangxifan
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0902d1e75a
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c++ string is not working, use char which is stable
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2019-06-13 18:38:46 -06:00 |
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tangxifan
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af1628abfe
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use bus port for primitives in Verilog generator
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2019-06-13 16:26:58 -06:00 |
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Baudouin Chauviere
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2019840d7c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |