tangxifan
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6122863548
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[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
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2021-10-09 20:44:28 -07:00 |
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tangxifan
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a1eaacf5a8
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[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
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2021-10-06 12:12:15 -07:00 |
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tangxifan
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b98a8ec718
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[Test] Added the dedicated test case for fixed shift register clock frequency
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2021-10-06 12:09:26 -07:00 |
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tangxifan
|
189ade6c1e
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[Test] Bug fix
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2021-10-05 19:17:34 -07:00 |
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tangxifan
|
f74ea5d39a
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[Test] Use the new openfpga shell script in don't care bit tests
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2021-10-05 19:14:44 -07:00 |
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tangxifan
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50604e4589
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[Test] move test cases
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2021-10-05 19:02:43 -07:00 |
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tangxifan
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fed6c133b1
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[Test] Add new tests to validate the correctness of bitstream files with don't care bits
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2021-10-05 18:59:33 -07:00 |
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tangxifan
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b21f212031
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[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
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2021-10-05 11:39:53 -07:00 |
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tangxifan
|
52569f808e
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[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
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2021-10-05 10:57:33 -07:00 |
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tangxifan
|
fa1908511d
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[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
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2021-10-04 16:36:20 -07:00 |
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tangxifan
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dda147e234
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[Flow] Add an example simulation setting file for defining programming shift register clocks
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2021-10-01 11:04:23 -07:00 |
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tangxifan
|
89a97d83bd
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[Test] Added a new test case for the shift register banks in QuickLogic memory banks
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2021-09-29 16:28:06 -07:00 |
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tangxifan
|
4400dae108
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[Test] Bug fix in the wrong arch name
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2021-09-28 11:40:25 -07:00 |
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tangxifan
|
dae3554fd4
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[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
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2021-09-28 11:27:49 -07:00 |
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tangxifan
|
655b195d8b
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[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
|
b0aaab9c03
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[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
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2021-09-22 11:32:13 -07:00 |
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tangxifan
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abfa380333
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[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
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tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
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2021-09-22 10:01:33 -07:00 |
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tangxifan
|
1412121541
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[Test] Added a new test to validate the fabric key parser for QL memory bank
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2021-09-21 16:20:24 -07:00 |
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tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
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2021-09-21 15:42:20 -07:00 |
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tangxifan
|
60fc3ab36c
|
[Test] Added a new test case for the WLR memory bank
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2021-09-20 11:20:36 -07:00 |
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tangxifan
|
b82cfdf555
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[Test] Add the QL memory bank test to regression test cases
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2021-09-09 09:29:21 -07:00 |
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tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
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2021-09-01 14:19:00 -07:00 |
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tangxifan
|
9f03ecb160
|
[Test] Patch test case due to the changes in counter benchmarks
|
2021-07-02 17:57:39 -06:00 |
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tangxifan
|
64dcdaec61
|
[Test] Update all the tasks that use counter benchmark
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2021-07-02 17:29:13 -06:00 |
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tangxifan
|
3cbe266c44
|
[Test] Bug fix on the test case for multi-mode FF and pin constraints
|
2021-07-02 15:27:27 -06:00 |
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tangxifan
|
3aacce2a96
|
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 14:04:42 -06:00 |
Ganesh Gore
|
edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
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tangxifan
|
5286f9ba25
|
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
|
2021-07-02 11:39:00 -06:00 |
ANDREW HARRIS POND
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006b54c4bc
|
ready for merge
|
2021-07-01 15:35:39 -06:00 |
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ANDREW HARRIS POND
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8513b8a4ff
|
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
|
2567fbee05
|
ready to merge
|
2021-07-01 15:28:59 -06:00 |
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tangxifan
|
04ceeefb0a
|
Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
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ANDREW HARRIS POND
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db9231c225
|
tests failing with initial blocks
|
2021-07-01 13:52:28 -06:00 |
komaljaved-rs
|
be14e4f448
|
added design_variables.yml
|
2021-07-01 16:31:42 +05:00 |
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komaljaved-rs
|
6559f71082
|
added ci_scripts
|
2021-07-01 15:07:37 +05:00 |
|
tangxifan
|
83d177b13b
|
[Test] Deploy the newly added adder benchmarks to tests
|
2021-06-30 15:14:24 -06:00 |
|
tangxifan
|
9eeec05a1f
|
[Test] Bug fix
|
2021-06-29 19:55:07 -06:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
2c1692e6dc
|
[Test] Bug fix
|
2021-06-29 17:54:25 -06:00 |
|
tangxifan
|
30c2f597f2
|
[Test] Added two cases to validate testbench generation without self checking
|
2021-06-29 16:06:15 -06:00 |
|
tangxifan
|
6f0600e17f
|
[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
|
2021-06-27 19:56:01 -06:00 |
|
tangxifan
|
477cba1c7e
|
Merge branch 'master' into verilog_testbench
|
2021-06-23 09:18:18 -06:00 |
|
tangxifan
|
f06017581c
|
[Test] Bug fix in counter micro benchmark tests
|
2021-06-22 16:33:50 -06:00 |
|
tangxifan
|
760570d883
|
[Test] Update counter test case for cover most counter HDL design
|
2021-06-21 18:13:18 -06:00 |
|
tangxifan
|
9c24a739be
|
[Test] Added a MAC benchmark sweeping test
|
2021-06-21 17:40:53 -06:00 |
Andrew Pond
|
3cfc42cdf9
|
added testbench CI
|
2021-06-15 14:16:31 -06:00 |
|
tangxifan
|
eed30605d7
|
[Test] patch test case
|
2021-06-09 15:20:55 -06:00 |