tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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8915d10d27
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add verbose output option to configure port disable timing writer
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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6177921d4c
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bug fixed in configure port disable timing. Now we disable the right ports of LUTs
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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f52b5d5b4c
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use error code in read_arch command
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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e9ceedb01b
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use constant openfpga context in SDC generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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067d09f954
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bug fix for configure port disable_timing writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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ae9f1fbd90
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critical bug fixed in the disable MUX output
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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99751b84f5
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bug fix in configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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02e86c565a
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bug fix in configuration chain SDC writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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4c0953415b
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add configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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dad99d13a2
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bug fixed in SDC timing writer for primitive pb_type
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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8d2360a710
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simplify include_netlist.v
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b8a79c563d
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bug fix in the SDC port generation
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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84d24ad075
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bug fix in pnr sdc grid writer for module paths in hierarchical view
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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99fa51cb49
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bug fixed in the SDC CB hierarchy writer
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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10e1a4b2fe
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format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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cc6d988872
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bug fix in grid SDC generator
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b167c85980
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fully expand grid hierarchy in SDC writer
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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55518f4cec
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minor fix in the sdc hierarchy writer for grids
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b57a90a6ca
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add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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5a8c05378e
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add --depth option to fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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d9dc7160a7
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minor fix on the hierarchy writer in SDC generator
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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17c254a370
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add missing file to follow up the previous commit
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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c651df6421
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add hierarchy writer to SDC generator
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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6aff33dd35
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add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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0985c720e9
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remove regexp in SDC generation.
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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8726c618eb
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add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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0e44cf3ea3
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now SDC to disable routing multiplexer outputs can use wildcards
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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609115e51f
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now hierarchical SDC generation is applicable to CB timing constraints
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7e82c23f52
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now add SDC generator supports both hierarchical and flatten in writing timing constraints
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7503c58fb2
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small fix on SDC generator for SB which do not exist in FPGA
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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d0793d9029
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now disable_sb_output support wildcard
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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8695c5ee78
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add options to use general-purpose wildcards in SDC generator
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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facd87dafe
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use wildcard in SDC generation for multiple-instanced-blocks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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1e2226e1c3
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now use explicit port mapping in the verilog testbenches for reference benchmarks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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69306faf22
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add a new include netlist for all the fabric-related netlists
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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87b17fc25f
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add netlist manager data structure
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2020-04-23 18:59:09 -06:00 |
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tangxifan
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bf841b9a8e
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bug fixed in identifying wired LUT
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2020-04-22 17:28:16 -06:00 |
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tangxifan
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8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
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73e9006372
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add arch file with spy pads
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2020-04-22 12:56:09 -06:00 |
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tangxifan
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9960625b01
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add example spypad architecture
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2020-04-22 11:10:59 -06:00 |
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tangxifan
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2e3054f79a
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bug fixed for SDC generation for LUTs
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2020-04-21 14:34:51 -06:00 |
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tangxifan
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68b7991a46
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bug fixed for sdc on memory blocks
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2020-04-21 13:37:56 -06:00 |
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tangxifan
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d325bede68
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add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
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3f1fb70d16
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FPGA SDC now constrain max and min delay for primitive modules in grids
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2020-04-21 11:00:28 -06:00 |
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tangxifan
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c2804a4c1f
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bug fix for RC delay computing in SDC generation
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2020-04-20 22:20:00 -06:00 |