tangxifan
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fff16a01ab
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[Test] Update tolerance when checking VTR benchmark QoR
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2021-03-23 12:27:20 -06:00 |
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tangxifan
|
781880ed93
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[Script] Add tolerance options to check qor script
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2021-03-23 12:26:33 -06:00 |
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tangxifan
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e3f8a6cf7a
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[Test] Deploy QoR check to VTR benchmark regression test
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2021-03-23 11:15:22 -06:00 |
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tangxifan
|
351dec5935
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[Test] Add QoR csv file for vtr benchmarks
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2021-03-23 11:15:02 -06:00 |
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tangxifan
|
23e7f7f1f5
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[Script] Update default list of result extraction for openfpga flow
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2021-03-23 11:06:42 -06:00 |
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tangxifan
|
adfbd28a7a
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[Script] Add a simple QoR checker
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2021-03-23 11:06:16 -06:00 |
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tangxifan
|
61eddb08de
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[Test] Update task configuration by commenting out high-runtime VTR benchmarks
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2021-03-22 14:42:42 -06:00 |
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tangxifan
|
55d1004cf2
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[Benchmark] Add missing DPRAM module to LU32PEEng
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2021-03-22 14:41:38 -06:00 |
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tangxifan
|
5fc83ebea3
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[Benchmark] Add missing DPRAM modules to LU8PEEng
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2021-03-22 14:38:00 -06:00 |
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tangxifan
|
b828f91a78
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[Benchmark] Add missing DPRAM and SPRAM modules to mcml
|
2021-03-22 14:13:05 -06:00 |
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tangxifan
|
d050f1b746
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[Script] Enable fast bitstream generation for VTR benchmarks
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2021-03-22 12:54:36 -06:00 |
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tangxifan
|
4bfd0c0a02
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[Test] Enable more VTR benchmark in testing
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2021-03-22 12:53:30 -06:00 |
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tangxifan
|
b906ab814e
|
[Benchmark] Add missing DPRAM module to mkPktMerge
|
2021-03-22 12:51:23 -06:00 |
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tangxifan
|
310c2a9495
|
[Benchmark] Add missing DPRAM module to mkDelayWorker32B
|
2021-03-22 12:51:02 -06:00 |
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tangxifan
|
707247283c
|
[Benchmark] Add missing DPRAM module to mkSMAdapter4B
|
2021-03-22 12:50:39 -06:00 |
|
tangxifan
|
eb056e2afd
|
[Benchmark] Add missing DPRAM module to or1200
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2021-03-22 12:50:17 -06:00 |
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tangxifan
|
7fd345a616
|
[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs
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2021-03-22 10:39:47 -06:00 |
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tangxifan
|
cc10b10703
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[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
|
2021-03-20 22:53:37 -06:00 |
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tangxifan
|
169ee53b79
|
[Benchmark] Add missing modules to VTR benchmarks
|
2021-03-20 22:53:17 -06:00 |
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tangxifan
|
eca2a35612
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[Script] Add route chan width option to vtr openfpga script
|
2021-03-20 22:00:09 -06:00 |
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tangxifan
|
9a3aff274f
|
[Test] Use fix routing channel width to save runtime for VTR benchmarks
|
2021-03-20 21:59:44 -06:00 |
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tangxifan
|
ca9a70fc88
|
[Test] Comment out benchmarks have problems in synthesis
|
2021-03-20 21:29:21 -06:00 |
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tangxifan
|
125e94a6b3
|
[Test] Add full VTR benchmark (with most commented); ready for massive testing
|
2021-03-20 21:01:18 -06:00 |
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tangxifan
|
2bd8ef2af9
|
[Benchmark] Patch boundtop.v with missing SPRAM module
|
2021-03-20 21:00:53 -06:00 |
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tangxifan
|
ee3677ecc1
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Merge branch 'master' into yosys_heterogeneous_block_support
|
2021-03-20 18:16:53 -06:00 |
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tangxifan
|
cb07848475
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[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
|
2021-03-20 18:11:54 -06:00 |
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tangxifan
|
f3792bc6f6
|
[Test] Update VTR benchmark test case to include DSP example benchmark
|
2021-03-20 18:09:19 -06:00 |
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tangxifan
|
477a522885
|
[HDL] Rename tech lib to be consistent with arch name changes
|
2021-03-20 18:08:03 -06:00 |
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tangxifan
|
911979a731
|
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
|
2021-03-20 18:04:59 -06:00 |
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tangxifan
|
1185f7b8bf
|
[Script] Add a template yosys script to enable DSP mapping
|
2021-03-20 17:05:30 -06:00 |
bbleaptrot
|
a6dfba4500
|
Update to try and display tutorial images
|
2021-03-19 16:29:25 -06:00 |
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bbleaptrot
|
e90bcdc4d5
|
Update to correctly include figure syntax
|
2021-03-19 16:21:45 -06:00 |
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bbleaptrot
|
05ec5186a2
|
Update to see if .. image:: works for images
|
2021-03-19 16:18:21 -06:00 |
|
bbleaptrot
|
4e363660e7
|
Update to correct syntax for images
|
2021-03-19 16:14:51 -06:00 |
|
bbleaptrot
|
eea73ca2bf
|
Add user_defined_templates.rst file
|
2021-03-19 16:10:46 -06:00 |
|
bbleaptrot
|
7b23231909
|
Add images for user_defined_templates.v tutorial
|
2021-03-19 16:08:50 -06:00 |
|
tangxifan
|
ed9b567d19
|
Merge branch 'master' into doc_patch
|
2021-03-18 22:34:43 -06:00 |
ganeshgore
|
35567fb3c3
|
Merge pull request #272 from lnis-uofu/yosys_heterogeneous_block_support
Yosys heterogeneous block support
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2021-03-18 16:17:55 -06:00 |
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tangxifan
|
73e37060a5
|
Merge branch 'master' into yosys_heterogeneous_block_support
|
2021-03-18 15:14:24 -06:00 |
|
tangxifan
|
3c1e3ed400
|
Merge branch 'master' into doc_patch
|
2021-03-18 15:14:05 -06:00 |
|
ganeshgore
|
a8f06db62f
|
Merge pull request #270 from lnis-uofu/netlist_name_patch
Name grid module pins in Verilog netlist with architecture port defintion
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2021-03-18 15:13:13 -06:00 |
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tangxifan
|
3ef292bdbb
|
Merge branch 'netlist_name_patch' of https://github.com/LNIS-Projects/OpenFPGA into netlist_name_patch
|
2021-03-17 20:28:40 -06:00 |
|
tangxifan
|
fa11410425
|
[Tool] Remove exceptions on outputing verilog port with lsb=0
|
2021-03-17 20:27:08 -06:00 |
|
tangxifan
|
d22d935322
|
[CI] Update regressiont tests run in CI script
|
2021-03-17 16:08:33 -06:00 |
|
tangxifan
|
6bf4880c50
|
[benchmark] Add vtr benchmark
|
2021-03-17 15:24:26 -06:00 |
|
tangxifan
|
7a986defba
|
[CI] Deploy vtr benchmark regression test to CI
|
2021-03-17 15:15:54 -06:00 |
|
tangxifan
|
f9dc7c1b54
|
[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
|
2021-03-17 15:15:22 -06:00 |
|
tangxifan
|
08a86e056a
|
[Test] Add vtr benchmark regression test
|
2021-03-17 15:13:58 -06:00 |
|
tangxifan
|
7eeb35d21f
|
[Script] Bug fix in yosys script to synthesis BRAM
|
2021-03-17 15:12:04 -06:00 |
|
tangxifan
|
1976a8068f
|
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
|
2021-03-17 15:11:17 -06:00 |