riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,807 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

3807 Commits

Author SHA1 Message Date
tangxifan c53c41b7a5 [Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file 2021-03-08 21:09:23 -07:00
tangxifan 131643dcc0 [Flow] Bug fix for yosys rewrite function in openfpga flow-run script 2021-03-08 21:08:55 -07:00
ganeshgore b860722893
Fixed parameter ys_rewrite_params name bug 2021-03-08 10:34:39 -07:00
ganeshgore 52de55e7eb
Merge branch 'master' into ganesh_dev 2021-03-08 10:15:06 -07:00
tangxifan a1aade5d01
Merge pull request #265 from lnis-uofu/shift_reg 
add shift register test case
 2021-03-08 09:49:22 -07:00
tangxifan 906d2fa72d
Merge branch 'master' into shift_reg 2021-03-08 09:24:29 -07:00
tangxifan f5a5f31a0e
Merge pull request #262 from lnis-uofu/add_yosys_options 
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically p…
 2021-03-08 09:23:24 -07:00
Ganesh Gore 7a35811430 [Flow] Yosys rewrite support 2021-03-08 00:35:47 -07:00
Ganesh Gore 67cd9a69b7 [Flow] Extended yosys variable subtitution 2021-03-08 00:21:07 -07:00
Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification 2021-03-07 22:25:01 -08:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Tarachand Pagarani ce76c58422 add shift register test case 2021-03-05 09:06:05 -08:00
Lalit Sharma 2b2acae757 Adding command to generate verilog file out of yosys run 2021-03-05 04:07:02 -08:00
Tarachand Pagarani d6464fa7cc update yosys submodule 2021-03-04 03:16:21 -08:00
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
Lalit Narain Sharma 57a4bccbac
Merge branch 'master' into add_yosys_options 2021-03-03 10:25:59 +05:30
tangxifan e6d1ac4a58
Merge pull request #260 from lnis-uofu/gg_ci_cd_dev 
[CI/CD] Skipped container login if branch is not master
 2021-03-02 08:46:49 -07:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
ganeshgore f0294d1339
Merge branch 'master' into gg_ci_cd_dev 2021-03-01 22:21:29 -07:00
Ganesh Gore 4eef4bd3d1 [CI/CD] Skipped container login if branch is not master 2021-03-01 17:47:02 -07:00
ganeshgore a162ee0661
Merge pull request #255 from lnis-uofu/default_net_type 
Support `default_nettype in Verilog generator
 2021-03-01 11:24:44 -07:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
tpagarani 8e89da5966
Merge pull request #256 from lnis-uofu/bump_yosys_1 
Bumping up latest yosys changes to yosys submodule
 2021-03-01 04:23:21 -05:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
Lalit Sharma 0038496d9c Replacing -openfpga with -family qlf_k4n8 2021-02-28 21:08:47 -08:00
Lalit Sharma ff7c9bb3c6 Bumping up latest yosys changes to yosys submodule 2021-02-28 20:55:55 -08:00
Lalit Narain Sharma c50eacd449
Merge pull request #252 from lnis-uofu/dev 
Add QuickLogic LUT adder test case
 2021-03-01 10:15:25 +05:30
tangxifan 521e1850c8 [Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1 2021-02-28 17:04:27 -07:00
tangxifan b4b6ada06f [Script] Correct bugs in example scripts using default_net_type 2021-02-28 16:31:44 -07:00
tangxifan 86930d63d3 [Test] Deploy new test to CI 2021-02-28 16:18:46 -07:00
tangxifan b90a17543d [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
tangxifan 73461971d2 [Tool] Bug fix for printing single-bit ports in Verilog netlists 2021-02-28 16:12:57 -07:00
tangxifan 9f4d05da67 [Test] Bug fix for new test case 2021-02-28 16:11:30 -07:00
tangxifan 8cc2c7d924 [Script] Bug fix for default net type example script 2021-02-28 12:35:44 -07:00
tangxifan 6d419fed41 [Test] Deploy verilog default net wire type test case to CI 2021-02-28 12:33:48 -07:00
tangxifan 18a7041424 [Test] Add default net type test for explicit port mapping 2021-02-28 12:31:32 -07:00
tangxifan 0723b79bce [Script] Add example script for verilog default net type 2021-02-28 12:29:56 -07:00
tangxifan 27200e3daa [Test] Update regression test cases for fpga verilog 2021-02-28 12:24:36 -07:00
tangxifan ff29cc3dff [Test] Move tests to a test group 2021-02-28 12:23:35 -07:00
tangxifan 9cb1ca42fe [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
tangxifan ae05871b1f [Script] Remove default net type from an example script; Limit it to some test cases 2021-02-28 12:19:14 -07:00
tangxifan d7eb159726 [Script] Add default net type option to example openfpga shell scripts 2021-02-28 12:08:30 -07:00
tangxifan c638e5bde5 [Doc] Update documentation for default net type option 2021-02-28 12:00:55 -07:00
tangxifan 15e26a5602 [Tool] Support default_net_type Verilog syntex in fabric generator 2021-02-28 11:57:40 -07:00
tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
tangxifan 744d87cb4e [Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues 2021-02-26 09:34:52 -07:00
tangxifan 870d3a0e27 Merge branch 'master' into dev 2021-02-26 09:28:42 -07:00
tpagarani 013f6d8497
Merge pull request #254 from lnis-uofu/update_yosys_scr_name 
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
 2021-02-26 04:28:12 -05:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
tpagarani d38514f87e
Merge pull request #253 from lnis-uofu/update_yosys_scr_name 
Modifying custom yosys script file name
 2021-02-26 02:37:09 -05:00