Commit Graph

75 Commits

Author SHA1 Message Date
tangxifan 5b0c9572c3 add mutators for delay_info 2019-08-07 21:19:16 -06:00
tangxifan 03a64e2ad8 complete the mutators for ports 2019-08-07 20:54:27 -06:00
tangxifan 9f8c7a3fc7 adding port mutators 2019-08-07 17:47:39 -06:00
tangxifan ed4642a23f adding basic mutators 2019-08-07 17:12:05 -06:00
tangxifan 38962c4607 adding member functions for circuit library 2019-08-07 15:45:27 -06:00
tangxifan 74da4ed51a start creating the class for circuit models 2019-08-07 11:38:45 -06:00
tangxifan fb2ca66ce9 start adding submodules of local encoders to multiplexer 2019-08-06 14:17:55 -06:00
tangxifan 33f3a991b5 init effort to start developing mux local encoders 2019-08-06 14:17:55 -06:00
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
AurelienUoU 19ccbce9d0 Rename option to use circuit_model rather than spice_model 2019-07-12 16:18:28 -06:00
tangxifan 3077efa74f add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
tangxifan 548242b368 plug-in tileable rr generator which can be enable by a XML property 2019-06-20 21:06:26 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
tangxifan 8c5ec4572d revert string to sprintf 2019-06-07 20:20:41 -06:00
tangxifan eef1312325 updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
tangxifan 502344b13a add missing files 2019-05-22 12:35:12 -06:00
tangxifan efbc454cdd Add Class for RRSwtichBlock and plug-in to replace the old t_sb 2019-05-22 12:34:06 -06:00
tangxifan b185a17359 add routing_channel unique module generation 2019-05-20 22:33:17 -06:00
Baudouin Chauviere a5a1a376ab Modified code for cleaner delay naming convention 2019-05-06 12:52:49 -06:00
tangxifan 4e3487b691 Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
tangxifan 70b66e0799 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 14:22:20 -06:00
tangxifan 11cf30b239 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 11:54:35 -06:00
tangxifan 5a97e3e602 update Makefile t 2019-05-03 11:48:41 -06:00