tangxifan
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b167c85980
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fully expand grid hierarchy in SDC writer
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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55518f4cec
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minor fix in the sdc hierarchy writer for grids
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b57a90a6ca
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add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints
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2020-06-11 19:31:05 -06:00 |
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Xifan Tang
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24934aff86
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update documentation on the depth option for fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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5a8c05378e
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add --depth option to fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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d9dc7160a7
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minor fix on the hierarchy writer in SDC generator
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2020-06-11 19:31:04 -06:00 |
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Xifan Tang
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752470c2da
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update documentation on write hierarchy command and options
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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17c254a370
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add missing file to follow up the previous commit
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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c651df6421
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add hierarchy writer to SDC generator
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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1943929353
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add write_fabric_hierarchy to regression tests
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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6aff33dd35
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add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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0985c720e9
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remove regexp in SDC generation.
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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98fbcb5410
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add time unit test for SDC generation to CI
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2020-06-11 19:31:04 -06:00 |
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Xifan Tang
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ac378febef
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update doc about time units in SDC generator
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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8726c618eb
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add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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47f040822f
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deploy the tests to CI
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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4083fae41a
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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2fbf9c2cfc
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change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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0e44cf3ea3
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now SDC to disable routing multiplexer outputs can use wildcards
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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609115e51f
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now hierarchical SDC generation is applicable to CB timing constraints
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2020-06-11 19:31:03 -06:00 |
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Xifan Tang
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d18e924a89
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Update documentation on new fpga_sdc option
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7e82c23f52
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now add SDC generator supports both hierarchical and flatten in writing timing constraints
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7503c58fb2
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small fix on SDC generator for SB which do not exist in FPGA
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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d0793d9029
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now disable_sb_output support wildcard
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2020-06-11 19:31:02 -06:00 |
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Xifan Tang
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ecdbdcb592
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update documentation on new SDC options
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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8695c5ee78
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add options to use general-purpose wildcards in SDC generator
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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facd87dafe
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use wildcard in SDC generation for multiple-instanced-blocks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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1e2226e1c3
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now use explicit port mapping in the verilog testbenches for reference benchmarks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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889bc8dbe8
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add more test cases about LUT design and deploy to CI
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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1d35ac8086
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deploy local encoder to CI
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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889f179ce7
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add local encoder test case
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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98a658a013
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bug fixed in routing_test.v. Deployed to regression tests
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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6dd8d347e1
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try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
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2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
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f6cea1e17c
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Added test_mode_low benchmark
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2020-06-11 19:31:01 -06:00 |
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CHARAS SAMY
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3c781b18d3
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Added routing benchmark
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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69306faf22
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add a new include netlist for all the fabric-related netlists
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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5c851a8467
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deploy the fabric/testbench generation only cases to travis
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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42cede37fa
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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a3fe6a9fcb
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update travis script with example run on MCNC big20
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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9bf91bd92a
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start testing mcnc_big20 using OpenFPGA tasks
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2020-06-11 19:30:55 -06:00 |
ganeshgore
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c31b20dc91
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Added support for simulation setting file in the task flow
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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49edeb119c
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BugFix : Relative path for refrence benchmark fixed
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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890ead91b9
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Fixed modelsim include references
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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c1b73efa62
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Added support for simulation setting file in the task flow
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2020-06-10 23:12:30 -06:00 |
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ganeshgore
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a3103f6afe
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BugFix : Relative path for refrence benchmark fixed
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2020-04-25 20:16:17 -06:00 |
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ganeshgore
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9d1b3d6865
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Fixed modelsim include references
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2020-04-24 21:53:57 -06:00 |
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ganeshgore
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9e46b4eb75
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-24 21:30:51 -06:00 |
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tangxifan
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185e574738
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removed redundant include files in all the verilog netlists except the top one
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2020-04-24 20:21:32 -06:00 |
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ganeshgore
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773790bc2c
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-24 11:00:40 -06:00 |