tangxifan
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e959821813
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[Tool] Enhance internal check functions for tile annotation
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2020-11-11 13:59:24 -07:00 |
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tangxifan
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4dc0fb81c5
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[Tool] Bug fix for clang compilation error
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2020-11-10 20:32:58 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
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67af145455
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[Tool] Add XML writer for tile annotation
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2020-11-10 14:51:46 -07:00 |
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tangxifan
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6fbdbe68ae
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[Tool] Add tile annotation parser
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2020-11-10 14:32:24 -07:00 |
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tangxifan
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0a273ffab6
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[Tool] Bug fix in the tight requirements on CCFF circuit model
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2020-11-06 11:16:46 -07:00 |
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tangxifan
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ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
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f1ce816d6c
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[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
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tangxifan
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e850dd5314
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[Tool] Relax checking codes for embedded I/O circuit models
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2020-11-02 13:54:31 -07:00 |
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tangxifan
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b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
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1e70825383
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[OpenFPGA Tool] Add XML syntax for configurable regions
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2020-09-28 13:51:43 -06:00 |
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tangxifan
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052b8b71c7
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[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
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2020-09-27 20:54:58 -06:00 |
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tangxifan
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491433fae2
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[OpenFPGA Tool] Update XML parser for fabric regions
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2020-09-27 20:41:01 -06:00 |
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tangxifan
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48b2bff0d9
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[OpenFPGA Tool] Update fabric key data structure to support regions
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2020-09-27 20:08:11 -06:00 |
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tangxifan
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94047037c5
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[OpenFPGA Tool] Streamline codes in openfpga arch parser
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2020-09-27 14:33:14 -06:00 |
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tangxifan
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51d96244c6
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[OpenFPGA Tool] Remove deprecated XML syntax
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2020-09-26 14:30:57 -06:00 |
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tangxifan
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8b8ce22fd1
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[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
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2020-09-23 20:37:28 -06:00 |
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tangxifan
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064678fe32
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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tangxifan
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f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
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8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
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c23742c751
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 20:13:27 -06:00 |
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tangxifan
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fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
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c31d36deb6
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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
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2020-09-14 16:16:03 -06:00 |
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tangxifan
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9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
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2020-08-23 14:06:03 -06:00 |
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tangxifan
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b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
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161d660837
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update documentation for the initial offset when mapping physical pins
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2020-08-19 15:00:46 -06:00 |
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tangxifan
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3eea12ceae
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added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
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2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
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35af0dd676
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streamline fabric bitstream file format
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2020-07-27 16:34:43 -06:00 |
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tangxifan
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92d2d2d849
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add fabric bitstream XML writer
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2020-07-26 21:00:57 -06:00 |
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tangxifan
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a3d22c56e3
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bug fix in FPGA-SPICE
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2020-07-24 19:51:32 -06:00 |
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tangxifan
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6d046efc52
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add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
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2020-07-24 16:25:27 -06:00 |
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tangxifan
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f573fa3ee0
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move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
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2020-07-22 18:47:12 -06:00 |
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tangxifan
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de4586217f
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now device binding is not mandatory for circuit models
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2020-07-14 12:04:22 -06:00 |
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tangxifan
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e2b492f184
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add circuit model tech binding
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2020-07-13 20:35:10 -06:00 |
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tangxifan
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62fd0947f5
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using a unified string to replace multi net names to save memory of bitstream database
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2020-07-08 16:28:20 -06:00 |
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tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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1ad6e8292a
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move constants from verilog domain to common so that FPGA-SPICE can share
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2020-07-05 11:39:46 -06:00 |
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tangxifan
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2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
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70d9678578
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reserve child block in bistream manager
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2020-07-03 14:04:10 -06:00 |
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tangxifan
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7d9c36aae1
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use length instead of msb in bitstream manager for block bits to save memory
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2020-07-03 12:06:15 -06:00 |
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tangxifan
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2783fda344
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use index range instead of vector for block bitstream
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2020-07-03 11:42:38 -06:00 |
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tangxifan
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6ea857ae6c
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use fast method to inquire number of bits and blocks in bitstream databases
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2020-07-03 10:55:25 -06:00 |
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tangxifan
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6397cbe9d2
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remove unused data in bitstream manager to compact memory usage
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2020-07-03 10:35:35 -06:00 |
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tangxifan
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246b4d5ac6
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reserve block bits to save memory
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2020-07-02 21:52:32 -06:00 |
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tangxifan
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043fb54206
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remove unused data in bitstream database
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2020-07-02 20:53:18 -06:00 |
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tangxifan
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9799fea48f
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optimizing bitstream storage
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2020-07-02 19:33:53 -06:00 |
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tangxifan
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dee4be96af
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reserve all the input/output net storage in bitstream manager
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2020-07-02 19:17:34 -06:00 |
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tangxifan
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f97e3bfba6
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add timer to openfpga shell
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2020-07-02 18:02:33 -06:00 |