tangxifan
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d325bede68
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add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
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3f1fb70d16
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FPGA SDC now constrain max and min delay for primitive modules in grids
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2020-04-21 11:00:28 -06:00 |
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tangxifan
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c2804a4c1f
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bug fix for RC delay computing in SDC generation
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2020-04-20 22:20:00 -06:00 |
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tangxifan
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1a8968cb37
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now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
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2020-04-20 21:12:51 -06:00 |
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tangxifan
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e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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2e3a811f4f
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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
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a7d900088b
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now generating simulation ini file will try to create directory first
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2020-04-15 20:53:37 -06:00 |
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tangxifan
|
72e8824a87
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bug fixed on removing undriven pins (direct connection between clbs) from cb
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2020-04-15 20:41:15 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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56e0d2a918
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critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
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2020-04-13 12:58:44 -06:00 |
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tangxifan
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e6c896d583
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now inout must be global port and I/O port so that it will appear in the top-level module
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2020-04-08 16:54:08 -06:00 |
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tangxifan
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b9dab2baaf
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add exit codes to command execution in shell context
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2020-04-08 16:18:05 -06:00 |
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tangxifan
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1fb37f4c71
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improve directory creator to support same functionality as 'mkdir -p'
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2020-04-08 12:55:09 -06:00 |
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tangxifan
|
0b1c8ac139
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bug fixed in identifying the physical interconnect for pb_graph nodes
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2020-04-07 19:46:42 -06:00 |
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tangxifan
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62276f9e28
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minor code format
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2020-04-07 18:43:11 -06:00 |
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tangxifan
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cbcd1d20d4
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fixed memory leakage in pb_pin fixup
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2020-04-07 16:24:04 -06:00 |
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tangxifan
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5a04da2082
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fix memory leakage in openfpga title
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2020-04-07 16:14:41 -06:00 |
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tangxifan
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26d1261c1f
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add test cases using shift registers
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2020-04-07 15:09:10 -06:00 |
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tangxifan
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92a3a444f9
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update VPR7 to support global I/O ports
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2020-04-06 20:44:00 -06:00 |
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tangxifan
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3369d724e9
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bug fixing in Verilog top-level testbench generation
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2020-04-05 17:50:11 -06:00 |
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tangxifan
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decc1dc4b2
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debugged global gp input/output port support
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2020-04-05 17:39:30 -06:00 |
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tangxifan
|
bcb86801fa
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bug fixed in gpio naming for module manager ports
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2020-04-05 17:26:44 -06:00 |
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tangxifan
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5f4e7dc5d4
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support gpinput and gpoutput ports in module manager and circuit library
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2020-04-05 16:52:21 -06:00 |
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tangxifan
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bc47b3ca94
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update verilog module writer to the global spy ports
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2020-04-05 16:04:13 -06:00 |
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tangxifan
|
8b583b7917
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debugging spy port builder in module manager
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2020-04-05 16:01:25 -06:00 |
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tangxifan
|
836f722f20
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start supporting global output ports in module manager
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2020-04-05 15:19:46 -06:00 |
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tangxifan
|
63306ce3a0
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add comments to explain the memory organization in the top-level module
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2020-04-01 11:05:30 -06:00 |
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tangxifan
|
ff9cc50527
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relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
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2020-03-27 20:09:50 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
|
4bf0a63ae6
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bug fixed for multiple io types defined in FPGA architectures
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2020-03-27 16:32:15 -06:00 |
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tangxifan
|
7c9c2451f2
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debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
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2020-03-27 16:03:42 -06:00 |
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tangxifan
|
329b0a9cf1
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add options to enable SDC constraints on zero-delay paths
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2020-03-25 15:55:30 -06:00 |
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tangxifan
|
4a0128f240
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minor fix on the SDC format
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2020-03-25 14:46:31 -06:00 |
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tangxifan
|
c2e5d6b8e2
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add options to dsiable SDC for non-clock global ports
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2020-03-25 14:38:13 -06:00 |
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tangxifan
|
787dc8ce83
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added ASCII OpenFPGA logo in shell interface
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2020-03-25 11:16:04 -06:00 |
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tangxifan
|
b6bdf78d95
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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tangxifan
|
9e4e12aae9
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fixed echo message in the compression rate of gsb uniquifying
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2020-03-22 16:13:04 -06:00 |
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tangxifan
|
ff474d87de
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fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
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2020-03-22 16:11:00 -06:00 |
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tangxifan
|
fdf6a6bd3e
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use chan_node_in_edges from rr_gsb in XML writer
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2020-03-22 15:48:11 -06:00 |
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tangxifan
|
3958ac2494
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fix bugs in flow manager on default compress routing problems
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2020-03-22 15:26:15 -06:00 |
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tangxifan
|
fc6abc13fd
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add physical tile utils to identify pins that have Fc=0
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2020-03-21 21:02:47 -06:00 |
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tangxifan
|
7b9384f3b2
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add write_gsb command to shell interface
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2020-03-21 19:40:26 -06:00 |
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tangxifan
|
637be076dc
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adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
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2020-03-21 18:49:20 -06:00 |
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tangxifan
|
9a518e8bb6
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bug fixed for tileable rr_graph builder for more 4x4 fabrics
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2020-03-21 18:07:00 -06:00 |
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tangxifan
|
c0e8d98c6f
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bug fixed in tile direct builder
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2020-03-21 12:43:56 -06:00 |
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tangxifan
|
8f35f191eb
|
use the formalized function in FPGA-SDC to identify direct connection
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2020-03-21 11:42:00 -06:00 |
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tangxifan
|
28123b8052
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remove the direct connected IPIN/OPIN from RR GSB builder
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2020-03-21 11:38:39 -06:00 |
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tangxifan
|
682b667a3c
|
minor bug fix for direct connection in FPGA-SDC
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2020-03-20 21:44:01 -06:00 |
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tangxifan
|
05ec86430a
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temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
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2020-03-20 17:56:03 -06:00 |
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tangxifan
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2c0c5a061b
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spot a bug in assigning rr_switch in tileable routing
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2020-03-20 16:53:43 -06:00 |