0aec30bac6
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
2021-04-19 15:53:33 -06:00
2c5634ee76
[Tool] Change pin naming of grid modules to be related to architecture port names
2021-03-13 20:05:18 -07:00
0c409b5bcc
[Tool] Add bitstream annotation support
2021-02-01 20:49:36 -07:00
4b77a3a574
[Tool] Now activity file is not a manadatory input of openfpga tools
2021-01-29 11:33:40 -07:00
b661c39b04
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
2020-12-02 19:36:36 -07:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
58807bfcb3
remove simulation settings from openfpga arch data structure
2020-06-11 19:31:16 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
b9dab2baaf
add exit codes to command execution in shell context
2020-04-08 16:18:05 -06:00
c0e8d98c6f
bug fixed in tile direct builder
2020-03-21 12:43:56 -06:00
aff73bdd74
deployed edge sorting and make it as an option to link_arch command
2020-03-08 15:59:53 -06:00
aa66042dfb
move simulation setting annotation to a separated source file
2020-02-29 15:19:02 -07:00
7b18f7cd09
now the auto select number of clocks in simulation is online
2020-02-29 13:29:16 -07:00
542fadaaae
allow users to use VPR critical path delay in OpenFPGA simulation
2020-02-28 12:10:27 -07:00
8e9660b816
add mapped block fast look-up as placement annotation
2020-02-24 16:09:29 -07:00
fdb27c5a6b
move lb_rr_graph construction to repack command
2020-02-20 13:24:34 -07:00
409b3f6896
add lb_rr_graph builder for the refactored version
2020-02-17 21:11:56 -07:00
539f13720a
tile direct supports inter-column/inter-row direct connections
2020-02-15 13:42:53 -07:00
213c611c0b
add tile direct builder
2020-02-14 22:21:32 -07:00
c78d3e9af1
add mux library builder
2020-02-12 14:58:23 -07:00
a736e09c29
add rr_switch binding in link openfpga arch command
2020-02-12 10:52:20 -07:00
a31d6c6d1e
rename pb_type annotation to device annotation
2020-02-12 09:52:18 -07:00
1372f748f1
put GSB builder online
2020-02-11 16:37:14 -07:00
99f5a86b49
bug fixed for routing annotation and routing net fix-up
2020-02-06 12:54:55 -07:00
dad204674b
done an initial version of clustering net fix-up based on routing results. Debugging on the way
2020-02-05 21:50:52 -07:00
75c3507acf
add verbose output option for openfpga linking architecture
2020-01-31 11:36:58 -07:00
d62c9fe86f
adding pb_graph_node annotation
2020-01-30 16:40:13 -07:00
8a7a4dc48e
add physical type annotation for interconnects and inference
2020-01-28 21:59:10 -07:00
5d9850c2eb
move pb_type annotation to independent source files as they are getting large
2020-01-28 15:13:14 -07:00
fdcc04cca8
add physical pb_type inference
2020-01-28 14:55:47 -07:00
caeb0bfff8
add physical pb_type binding for explicit annotations
2020-01-28 14:27:35 -07:00
82f71e82e8
add check codes for physical mode annotation for pb_types
2020-01-27 21:15:32 -07:00
f99dd4c261
debugged pb_type physical mode annotation
2020-01-27 20:40:18 -07:00
b8c504f574
Do not allow vpr to free everything when it is done. So that we can have access to their device data
2020-01-27 19:49:05 -07:00
df056f5d70
openfpga shell will stay in interactive mode after executing a script
2020-01-27 17:56:24 -07:00
5ecb771673
debugging the annotation to physical mode of pb_types
2020-01-27 17:43:22 -07:00
a6fbbce33e
start developing the openfpga arch binding to vpr
2020-01-27 15:31:12 -07:00
tangxifan