tangxifan
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d64aeef5c4
|
add profiling to routing compact process
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2019-07-03 16:57:34 -06:00 |
|
tangxifan
|
1a1da30ae9
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fixed a critical bug in using tileable route chan W
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2019-07-03 16:46:43 -06:00 |
|
tangxifan
|
b79d276ea9
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add profiling to fpga_x2p_setup
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2019-07-03 14:44:54 -06:00 |
|
tangxifan
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d5137eb424
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-03 14:31:18 -06:00 |
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tangxifan
|
5195faab8b
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Merge branch 'dev' into tileable_routing
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2019-07-03 14:30:39 -06:00 |
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tangxifan
|
4f3cb0bdf3
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added tileable routing chanW adaption to fixed W router
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2019-07-03 14:29:50 -06:00 |
Ganesh Gore
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443a73954f
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Removed all local files
+ Removed local configurations and scripts from previous commit
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2019-07-03 14:26:06 -06:00 |
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Ganesh Gore
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57ad71438b
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Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
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2019-07-03 13:39:52 -06:00 |
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tangxifan
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0c3e8bb70a
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add a new option to the router to enable conversion of route_chan_width to be tileable
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2019-07-03 12:11:48 -06:00 |
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tangxifan
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02398818a9
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update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
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2019-07-03 10:33:02 -06:00 |
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tangxifan
|
4392c6bc3a
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bug fixing in fpga_flow scripts and add more print-out message for VPR
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2019-07-02 15:34:59 -06:00 |
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tangxifan
|
95674c4687
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added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
|
tangxifan
|
44301bfd77
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updated SPICE generator to avoid issues on clb2clb_direct
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2019-07-02 09:01:52 -06:00 |
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tangxifan
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5b25bbb120
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bug fixed for direct connection in CBs and direct connection in top netlist
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2019-07-01 17:25:00 -06:00 |
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tangxifan
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1332ba62e8
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update tileable rr_graph generator to improve routability and also enable assoicated testing
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2019-06-27 17:52:25 -06:00 |
|
tangxifan
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15c536e9b4
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minor fixing in printing the rr_node stats
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2019-06-27 16:34:21 -06:00 |
|
Ganesh Gore
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11e6350214
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Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev
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2019-06-27 14:22:40 -06:00 |
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tangxifan
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8edd85c9fc
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keep fixing bugs in verilog SDC generator for tileable CBs
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2019-06-26 22:58:52 -06:00 |
|
tangxifan
|
711e369fe7
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fixing bugs in the SDC generator and report_timing
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2019-06-26 18:09:09 -06:00 |
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tangxifan
|
0fe54d87d5
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fixed a bug in SDC generator for constraining SBs in tileable arch
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2019-06-26 17:06:14 -06:00 |
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tangxifan
|
7d85eb544d
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start fixing bugs for SDC generator when using tileable arch
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2019-06-26 16:48:17 -06:00 |
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tangxifan
|
f5920c7422
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fix bugs in ptc_num using for SB
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2019-06-26 16:21:02 -06:00 |
|
tangxifan
|
3d8200e217
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critical bug fixed in bitstream generator for compact routing hierarchy
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2019-06-26 15:51:11 -06:00 |
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tangxifan
|
d2ed82d14d
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 15:00:39 -06:00 |
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tangxifan
|
57616361c2
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fixed critical bugs in cb configuration port indices
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2019-06-26 14:58:52 -06:00 |
Baudouin Chauviere
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d2bd2be76b
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Warnings correction in the make sequence
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2019-06-26 14:33:12 -06:00 |
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tangxifan
|
42f85004b6
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fix bugs in finding the ending SB of a rr_node
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2019-06-26 14:13:41 -06:00 |
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tangxifan
|
9b6a4b39bb
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Merge branch 'tileable_routing' into multimode_clb
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2019-06-26 11:36:08 -06:00 |
|
tangxifan
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c879e7f6c5
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fixed a critical bug when instanciating Connection blocks
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2019-06-26 11:33:02 -06:00 |
|
Baudouin Chauviere
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b7c2954b91
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-26 10:51:55 -06:00 |
|
Baudouin Chauviere
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8f21a3b177
|
Memory leakage correction
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2019-06-26 10:50:38 -06:00 |
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tangxifan
|
d50fb7ee19
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
AurelienUoU
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ec504049ef
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Update Testbenches to increase accuracy + commented compact routing option until debug
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2019-06-26 10:01:12 -06:00 |
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tangxifan
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a3670bb752
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-26 09:45:04 -06:00 |
|
Baudouin Chauviere
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56557b94e7
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Bug Fix
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2019-06-26 08:53:46 -06:00 |
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tangxifan
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3c0ef2067d
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fixed critical bugs in pass_tracks identification and update regression test for tileable arch
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2019-06-25 21:59:38 -06:00 |
|
Baudouin Chauviere
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bb250ddef9
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Bug fix in cpp
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2019-06-25 16:47:10 -06:00 |
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Ganesh Gore
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6d3066174b
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Merge remote-tracking branch 'origin/fpga_spice' into ganesh_dev
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2019-06-25 15:12:13 -06:00 |
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tangxifan
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4d3b5f12b4
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fixed bugs for UNIVERSAL and WILTON switch blocks
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2019-06-25 14:15:29 -06:00 |
|
Baudouin Chauviere
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332ce17f03
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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tangxifan
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a88263a4c2
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update rr_block writer to include IPINs in XML files
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2019-06-25 11:17:22 -06:00 |
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tangxifan
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785b560bd5
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sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
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2019-06-24 22:46:56 -06:00 |
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tangxifan
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fd301eeb66
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many bug fixing and now start improving the routability of tileable rr_graph
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2019-06-24 17:33:29 -06:00 |
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tangxifan
|
0d62661c71
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bug fixing and spot critical bugs in directlist parser
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2019-06-23 20:52:38 -06:00 |
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tangxifan
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cdd4af9c58
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vpr likes the tileable rr_graph while fpga_x2p does not
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2019-06-23 18:11:13 -06:00 |
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tangxifan
|
59df305668
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bug fixing and reorganize rr_graph builder source files
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2019-06-23 16:40:13 -06:00 |
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tangxifan
|
2837f44df2
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bug fixing for tileable rr_graph generator.
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2019-06-22 20:41:06 -06:00 |
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tangxifan
|
7c38b32eb1
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keep bug fixing for tileable rr_graph generator
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2019-06-21 22:51:11 -06:00 |
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tangxifan
|
1b91c32121
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Merge branch 'multimode_clb' into tileable_routing
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2019-06-21 17:59:55 -06:00 |
|
tangxifan
|
41954056ce
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many bug fixing for tileable rr_graph generator. Still debugging
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2019-06-21 17:58:46 -06:00 |