tangxifan
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f002f7e30f
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add const 0 and 1 module Verilog generation
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2019-10-21 14:17:09 -06:00 |
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tangxifan
|
bd37f0d542
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correct bugs in decoder data port alignment to memory ports of multiplexing structure
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2019-10-21 13:16:15 -06:00 |
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tangxifan
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fe433f3e50
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bug fixed for local encoders and module nets creation
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2019-10-21 12:23:00 -06:00 |
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tangxifan
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b2f57ecf81
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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tangxifan
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520e145af2
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
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tangxifan
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04f0fbebf7
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plug in module graph to feed verilog writers
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2019-10-18 21:59:22 -06:00 |
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tangxifan
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b1cafcdbde
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add missing files
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2019-10-18 21:04:35 -06:00 |
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tangxifan
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fbe56a06c4
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add decoder module builders
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2019-10-18 21:01:10 -06:00 |
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tangxifan
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7c1bce4b59
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add module builders for essential gates
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2019-10-18 20:41:05 -06:00 |
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tangxifan
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3b82d62d03
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start developing module graph builders
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2019-10-18 20:02:02 -06:00 |
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tangxifan
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db38f21412
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add netlist manager class
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2019-10-18 17:59:03 -06:00 |
|
tangxifan
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8c1158fc5c
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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tangxifan
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cfec8d70ab
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improved refactoring on clb2clb connection by considering flexible arch
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2019-10-18 11:20:09 -06:00 |
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tangxifan
|
4171a674b1
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refactored clb2clb direct connects for cross-column/row
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2019-10-17 23:06:59 -06:00 |
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tangxifan
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190449c06f
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refactoring top-level module with clb2clb direct connection
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2019-10-17 17:29:04 -06:00 |
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tangxifan
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945e138e62
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debugged the gsb-grid connection in top module.
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2019-10-15 22:02:25 -06:00 |
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tangxifan
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c9d8311a93
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bug fixing for grid-gsb connections in top module when using compact routing
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2019-10-15 18:00:55 -06:00 |
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tangxifan
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6a13120208
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rename grid modules to be clear
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2019-10-15 16:28:46 -06:00 |
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tangxifan
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071757dc52
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add module nets to connect grids and sbs
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2019-10-15 16:08:51 -06:00 |
Ganesh Gore
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c034b871bb
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Made activity file independent of power option
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2019-10-15 16:08:25 -06:00 |
|
Ganesh Gore
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eaf8ecee86
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added _vpr.txt subscript to vpr log files
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2019-10-15 16:07:34 -06:00 |
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tangxifan
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4b56b755f2
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refactored instanciation of routing modules in top module
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2019-10-14 21:06:10 -06:00 |
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tangxifan
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bd6a0c6a55
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refactored grid instance addition to top module
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2019-10-14 17:47:10 -06:00 |
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tangxifan
|
f779ad7ecf
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bug fixing for global and gpio port wiring; start refactoring top-level module
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2019-10-14 15:53:04 -06:00 |
|
tangxifan
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6793c67c8d
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refactored pb_type and grid Verilog generation
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2019-10-13 21:07:30 -06:00 |
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tangxifan
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b581399761
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add memory ports and nets to intermediate pb_types
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2019-10-13 17:45:32 -06:00 |
|
tangxifan
|
cab4bd6807
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add gpio ports to pb_type modules
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2019-10-13 16:23:22 -06:00 |
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tangxifan
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0f50251b3b
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add mux and associated memory modules in refactoring Verilog generation for pb_types
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2019-10-13 11:11:19 -06:00 |
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tangxifan
|
85644d07ae
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refactoring pb interc Verilog generation
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2019-10-12 21:55:53 -06:00 |
|
tangxifan
|
a65b76c25a
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Merge branch 'dev' into refactoring
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2019-10-12 18:24:03 -06:00 |
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tangxifan
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08df0fd585
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Merge pull request #30 from LNIS-Projects/master
Update README from Tim
|
2019-10-12 11:19:05 -06:00 |
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tangxifan
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d1948c82eb
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Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
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2019-10-11 21:43:47 -06:00 |
|
tangxifan
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49a8273482
|
Merge pull request #29 from mithro/patch-1
Small formatting fixes to the README
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2019-10-11 20:16:56 -06:00 |
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tangxifan
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b3ca0d32a4
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remove configuration bus naming dependency on SRAM circuit models
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2019-10-11 19:47:36 -06:00 |
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tangxifan
|
73a5977e0d
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Debugged Verilog generation for primitive pb_types
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2019-10-11 18:00:37 -06:00 |
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tangxifan
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50f7d1eae3
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bug fixing in Verilog port merging and instanciation
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2019-10-11 14:20:04 -06:00 |
|
tangxifan
|
663b1b7665
|
refactorint net addition for configuration signals in module graph
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2019-10-11 13:07:14 -06:00 |
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tangxifan
|
c9950162d1
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start plug in new Verilog writer. Start debugging
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2019-10-10 22:02:46 -06:00 |
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tangxifan
|
1f650aac73
|
add local direct connection Verilog code generation
|
2019-10-10 20:54:31 -06:00 |
Tim Ansell
|
916cfa27ed
|
Small formatting fixes to the README
* Make the compile steps easy to copy.
* Small wording fixes.
* Use relative links (github rewrites them).
* Remove unneeded `<br>` tags.
|
2019-10-10 19:39:44 -07:00 |
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tangxifan
|
f2b3341d87
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
|
tangxifan
|
e5956467fd
|
developing verilog writer for modules
|
2019-10-10 14:43:32 -06:00 |
|
tangxifan
|
edad988ebb
|
add net accessor and mutators to module manager
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2019-10-09 21:14:30 -06:00 |
|
tangxifan
|
557d8b60f3
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start implementing module graph-based connection
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2019-10-09 20:30:16 -06:00 |
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tangxifan
|
9cb6e64ab3
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refactoring instanciation inside primitive pb_type Verilog module
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2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
|
add wire connection in Verilog module declaration
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2019-10-08 20:14:38 -06:00 |
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tangxifan
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6bed89c237
|
refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
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2019-10-08 18:00:04 -06:00 |
|
tangxifan
|
ea2942640e
|
refactored port addition for pb_types in Verilog generation
|
2019-10-08 14:03:17 -06:00 |
|
tangxifan
|
512e9f4e8e
|
refactoring Verilog generation for primitive pb_types
|
2019-10-08 12:10:26 -06:00 |
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tangxifan
|
173b886314
|
add module name generation for pb_types
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2019-10-07 21:09:54 -06:00 |