Lalit Sharma
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ea4aee8cb2
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
|
Lalit Sharma
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0038496d9c
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Replacing -openfpga with -family qlf_k4n8
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2021-02-28 21:08:47 -08:00 |
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Lalit Sharma
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1082d3c677
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Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
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2021-02-25 23:39:07 -08:00 |
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Lalit Sharma
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1e48d4f6dc
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Modifying custom yosys script file name
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2021-02-25 22:21:39 -08:00 |
Ganesh Gore
|
df4a397470
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[Cleanup] Removed deadcode
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2021-02-03 10:35:14 -07:00 |
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Lalit Sharma
|
ebe66dea35
|
Bumping up latest yosys changes related to adder tech mapping
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2021-02-03 14:30:06 +05:30 |
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Lalit Sharma
|
8a5741b1ae
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Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
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2021-01-08 07:08:24 -08:00 |
|
Lalit Sharma
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3c9e4919b4
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Updating variable name in ys to call BLIF output file.
|
2020-12-18 03:18:46 -08:00 |
|
Lalit Sharma
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1f994319fd
|
Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
|
2020-12-16 04:19:56 -08:00 |
|
Lalit Sharma
|
891e2f8aa3
|
Adding arch xml from SOFA repo. Also updating the script with its file location
|
2020-12-16 04:14:18 -08:00 |
|
Lalit Sharma
|
0ee3efb306
|
Adding a testcase to run yosys quicklogic flow
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2020-12-10 02:41:43 -08:00 |
Andrew Lukefahr
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2d92a1f1af
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Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
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ganeshgore
|
890ead91b9
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Fixed modelsim include references
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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ea4122a8a4
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Updated openfpga_flow and task file to support sheel run
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2020-04-06 00:34:36 -06:00 |
AurelienUoU
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09fd2afa9c
|
Adding heterogeneous synthesis requirements
|
2019-12-03 16:09:26 -07:00 |
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Ganesh Gore
|
f05aede868
|
Added task support for modelsim script
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2019-11-15 23:23:15 -07:00 |
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Ganesh Gore
|
27005d6640
|
Added Modelsim Python Script
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2019-11-01 18:20:40 -06:00 |
|
Ganesh Gore
|
d269472daf
|
Updated formality python script
|
2019-09-27 14:00:57 -06:00 |
|
Ganesh Gore
|
d64bb18346
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
Ganesh Gore
|
f558437ae1
|
Added task for vpr_blif flow
|
2019-08-25 00:23:39 -06:00 |
|
Ganesh Gore
|
30cbe38d3d
|
Added Test Modes - Added blif VPR Option
|
2019-08-22 17:00:59 -06:00 |
|
Ganesh Gore
|
afee2229af
|
Removed unused templates and file from openfpga_flow directory
|
2019-08-19 21:32:52 -06:00 |
|
Ganesh Gore
|
08b0ef3550
|
Updated validate_command_line_arguments function
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
|
2019-08-19 21:28:23 -06:00 |
|
Ganesh Gore
|
616d7706c9
|
Added list of intermidiate files filename
|
2019-08-19 19:05:08 -06:00 |
|
Ganesh Gore
|
8f8707ff98
|
Added option to filter results after parsing
|
2019-08-19 19:04:14 -06:00 |
|
Ganesh Gore
|
cb5b16c949
|
Moved required files to openfpga folder
|
2019-08-19 18:57:42 -06:00 |
|
Ganesh Gore
|
5d3708651e
|
Added fpga_flow and fpga_task script
+ Missed local intermediate commits
|
2019-08-15 14:39:58 -06:00 |
|
Ganesh Gore
|
9ab57d1b2e
|
Added fpga_flow script - Working Yosys
|
2019-08-09 16:49:05 -06:00 |
|
Ganesh Gore
|
b82369dd96
|
Added first draft of fpga_task script
|
2019-08-09 00:17:06 -06:00 |