Xifan Tang
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61e359efc5
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Enable an option to disable/enable graphics in VPR compilation
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2019-06-08 15:08:17 -06:00 |
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tangxifan
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90696def6d
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remove vpr Makefile
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2019-06-07 23:44:39 -06:00 |
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tangxifan
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d737c4ff46
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fix path in regression test! TODO: must keep a duplicated copy for template.xml
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2019-06-07 23:31:42 -06:00 |
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tangxifan
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3ad4a33751
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update travis to use gcc8 and disable graphics for vpr when compile in osx
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2019-06-07 22:38:21 -06:00 |
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tangxifan
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e8d52121c6
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try j16 for travis in linux
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2019-06-07 22:32:47 -06:00 |
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tangxifan
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1b02428c04
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change travis gcc and gxx setting
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2019-06-07 22:25:55 -06:00 |
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tangxifan
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f5b6ee6adf
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update travis configuration and clean up repository
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2019-06-07 22:19:11 -06:00 |
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tangxifan
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1f228dd42b
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Merge branch 'tileable_sb' into multimode_clb
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2019-06-07 20:23:32 -06:00 |
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tangxifan
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8c5ec4572d
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revert string to sprintf
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2019-06-07 20:20:41 -06:00 |
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tangxifan
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a55c577a61
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-07 18:56:32 -06:00 |
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tangxifan
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0f1ed19ad0
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Revert to the use of sprintf instead std::string. Have no idea why string is not working
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2019-06-07 18:54:57 -06:00 |
AurelienUoU
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345a081eff
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Correct error of target to rewrite file in regression test
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2019-06-07 17:37:56 -06:00 |
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tangxifan
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44ce0e8834
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update gsb unique module detection and fix formal verification port direction
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2019-06-07 17:18:38 -06:00 |
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tangxifan
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24d53390d8
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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tangxifan
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c9f810ceb6
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update rr_gsb to build connection blocks
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2019-06-07 11:01:55 -06:00 |
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tangxifan
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472aff5acb
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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tangxifan
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ce9fc5696c
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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tangxifan
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8c1e7b799f
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fixed critical bugs in Connection Block Unique Module detection
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2019-06-06 16:31:50 -06:00 |
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tangxifan
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4f543c510c
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-06-06 12:50:03 -06:00 |
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tangxifan
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873e4d989f
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fine-tuning Verilog format and node addition to rr_blocks
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2019-06-06 12:48:41 -06:00 |
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AurelienUoU
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182d49da45
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Update regression test scripts
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2019-06-06 11:47:51 -06:00 |
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tangxifan
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c2de0eefb1
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fix redundant comma in SB Verilog module
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2019-06-06 09:15:05 -06:00 |
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tangxifan
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b9e1b1afc4
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fix a critical bug in num_reserved_sram_ports
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2019-06-05 17:31:01 -06:00 |
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tangxifan
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aaf8d23971
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fix critical bugs in routing submodules
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2019-06-05 16:43:18 -06:00 |
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tangxifan
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01e075377d
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fix typo in Verilog generation
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2019-06-05 15:30:34 -06:00 |
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tangxifan
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21d0cb52bc
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Merge remote-tracking branch 'origin' into tileable_sb
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2019-06-05 13:31:49 -06:00 |
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tangxifan
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24ca3104b0
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fix minor bugs in Switch Block submodules
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2019-06-05 13:30:55 -06:00 |
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tangxifan
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0f87ae9886
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support switch block submodule Verilog generation by segments
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2019-06-05 12:56:05 -06:00 |
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AurelienUoU
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84fabbd43b
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Fix sdc analysis bug related to virtual nodes + add the option in regression test
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2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
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d24488092d
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Fix bug
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2019-06-05 11:40:04 -06:00 |
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tangxifan
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c2d8fa00ba
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add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
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AurelienUoU
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fcc10d8acf
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Correct fpga_flow/arch/template files
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2019-06-04 16:45:04 -06:00 |
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AurelienUoU
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a2f6ded2a2
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Add path modification in file changing a keyword into OpenFPGA full path
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2019-06-04 15:21:15 -06:00 |
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tangxifan
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98b82c17be
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bug fixing for clear RRSwitchBlock
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2019-06-04 14:02:49 -06:00 |
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tangxifan
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2c6780ab92
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add side mirror detection for RRSwitchBlock
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2019-06-04 13:01:22 -06:00 |
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AurelienUoU
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eb72cb201c
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Use debug cmake build type to avoid building error
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2019-06-03 15:34:26 -06:00 |
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AurelienUoU
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6974a4618f
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Test gcc6 cmake3.13
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2019-06-03 14:53:52 -06:00 |
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AurelienUoU
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f51aa41c23
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Correct gcc instantiation
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2019-06-03 14:13:22 -06:00 |
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AurelienUoU
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c87c349c75
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Test gcc6/cmake3.5
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2019-06-03 13:58:00 -06:00 |
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AurelienUoU
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f4b8c3cf25
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Try another combination cmake/gcc
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2019-06-03 13:45:34 -06:00 |
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AurelienUoU
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ab9834798a
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Test if travis issue is the same as spotted on VM
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2019-06-03 12:01:37 -06:00 |
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AurelienUoU
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8a5ff37262
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Verify cmake version called to build
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2019-06-03 11:16:39 -06:00 |
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AurelienUoU
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813470d459
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Test Cmake fix
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2019-06-03 10:31:44 -06:00 |
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AurelienUoU
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4523bd21e9
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Update version of cmake causing trouble
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2019-06-03 10:21:24 -06:00 |
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AurelienUoU
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7368e6d7e4
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-31 11:01:07 -06:00 |
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AurelienUoU
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737300eb54
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Fix regression test
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2019-05-31 11:00:30 -06:00 |
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Baudouin Chauviere
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1932d00309
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Correction of the SDC to remove global clocks
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2019-05-30 15:04:21 -06:00 |
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AurelienUoU
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ba05a08ef0
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Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
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2019-05-30 09:52:19 -06:00 |
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AurelienUoU
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0e820d38ea
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Speedup the install on travis
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2019-05-29 16:53:35 -06:00 |
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AurelienUoU
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46fa1197b0
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Test reading tech file
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2019-05-29 16:43:56 -06:00 |