tangxifan
|
9b0617ffe6
|
[Tool] Bug fix for mappable I/O support
|
2020-11-04 20:45:51 -07:00 |
|
tangxifan
|
a6c7bb2c48
|
[Arch] Update OpenFPGA arch for new syntax on I/O
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2020-11-04 20:24:02 -07:00 |
|
tangxifan
|
37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
dd86f7f464
|
[Arch] Path architecture for caravel i/o interface
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2020-11-04 17:16:21 -07:00 |
|
tangxifan
|
c074e88dcd
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[HDL] Add embedded I/O HDL for Caravel SoC interface
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2020-11-04 17:09:59 -07:00 |
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tangxifan
|
aebf7453d0
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[Arch] Add architecture files with compatible I/O capacity with caravel SoC
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2020-11-04 16:57:00 -07:00 |
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tangxifan
|
19f2bf9b38
|
[Test] deploy new test cases to CI
|
2020-11-04 16:35:51 -07:00 |
|
tangxifan
|
61376a2979
|
[Test] Add test cases for various tile organization
|
2020-11-04 16:32:52 -07:00 |
|
tangxifan
|
cf455df555
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[Arch] Add architecture for bottom-right and top-left tile organization
|
2020-11-04 16:24:36 -07:00 |
|
tangxifan
|
46ca406f10
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[Arch] Add a new vpr architecture with new tile organization
|
2020-11-04 16:20:01 -07:00 |
|
tangxifan
|
049ca14461
|
[Doc] Add new naming rules for vpr architecture files
|
2020-11-04 16:17:56 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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1f3e656f2e
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Merge pull request #115 from LNIS-Projects/dev
Refactor the codes for walking through io blocks
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2020-11-04 12:54:07 -07:00 |
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tangxifan
|
4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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5d41cc6d23
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Merge pull request #114 from LNIS-Projects/dev
Support I/O interfaces for Embedded FPGAs
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2020-11-02 21:10:52 -07:00 |
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tangxifan
|
c036c87d6d
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[HDL] Bug fix in the GP output pad
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2020-11-02 18:37:53 -07:00 |
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tangxifan
|
1e47203c7c
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[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
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2020-11-02 18:35:26 -07:00 |
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tangxifan
|
e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
|
1fd899ecee
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[Tool] Relex logic block checking codes to skip zero-capacity nodes
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2020-11-02 16:57:19 -07:00 |
|
tangxifan
|
3b49e6d090
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[Arch] Patch embedded IO architecture by forcing only 1 pad per block
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2020-11-02 15:39:31 -07:00 |
|
tangxifan
|
c512644a09
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[Arch] Patch embedded I/O example architecture
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2020-11-02 15:16:19 -07:00 |
|
tangxifan
|
7e9e0ec9d4
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[HDL] Bug fix in I/O HDL code
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2020-11-02 15:15:45 -07:00 |
|
tangxifan
|
f1ce816d6c
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[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
|
tangxifan
|
2f237a6240
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[HDL] Add HDL codes for embedded I/Os
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2020-11-02 14:01:27 -07:00 |
|
tangxifan
|
55b77ac6cb
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[Arch] Bug fixed in embedded FPGA architecture
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2020-11-02 13:57:15 -07:00 |
|
tangxifan
|
e850dd5314
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[Tool] Relax checking codes for embedded I/O circuit models
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2020-11-02 13:54:31 -07:00 |
|
tangxifan
|
a7e7fa2005
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[Arch] Update arch with true embedded I/O definition
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2020-11-02 13:29:40 -07:00 |
|
tangxifan
|
65ca53ac98
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[Test] Update test case with the new arch name
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2020-11-02 13:16:42 -07:00 |
|
tangxifan
|
8c8190047f
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[Arch] Rename architecture files for embedded I/Os
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2020-11-02 13:15:19 -07:00 |
|
tangxifan
|
a346c529aa
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[Test] Deploy test case to CI
|
2020-11-02 12:29:20 -07:00 |
|
tangxifan
|
bc00dee858
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[Test] Add test case for embedded I/O
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2020-11-02 12:28:25 -07:00 |
|
tangxifan
|
f86f43d287
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[Arch] Add openfpga architecture file for constrained pin equivalence
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2020-11-02 12:27:40 -07:00 |
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tangxifan
|
795b30f76b
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[Arch] Add VPR architecture with partial pin equivalence
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2020-11-02 11:54:25 -07:00 |
|
tangxifan
|
032cbfb8b2
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Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
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2020-10-31 10:37:38 -06:00 |
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tangxifan
|
be7f7592ae
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[Doc] Update documentation about don't care bit in frame address
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2020-10-30 22:13:28 -06:00 |
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tangxifan
|
6b25cf720d
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[Tool] Comment on the memory efficiency on fabric bitstream address storage
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2020-10-30 22:09:48 -06:00 |
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tangxifan
|
7e940980e1
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[Doc] Update documentation about configuration regions for frame-based protocol
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2020-10-30 21:52:01 -06:00 |
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tangxifan
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940eb937f2
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[Test] add multi-region configuration frame test cases to CI
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2020-10-30 21:21:11 -06:00 |
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tangxifan
|
b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
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5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
|
4c14428400
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[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
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2020-10-30 10:50:00 -06:00 |
|
tangxifan
|
ca7d43275d
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[Test] Add test case for multi_region configuration frame
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2020-10-30 10:48:29 -06:00 |
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tangxifan
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29da368742
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[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
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2020-10-30 10:46:47 -06:00 |
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tangxifan
|
b701bd2640
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[Arch] Add multi-region architecture example for frame-based protocol
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2020-10-30 10:45:14 -06:00 |
|
tangxifan
|
0d77916041
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[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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cd0d3dd798
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Merge pull request #112 from LNIS-Projects/dev
Multi-region Memory Bank Configuration Protocol Support
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2020-10-29 18:39:44 -06:00 |
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tangxifan
|
1d930d1b5d
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[Architecture] Add missing arch files and bug fix
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2020-10-29 18:08:26 -06:00 |
|
tangxifan
|
8ef6ae32fb
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[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
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2020-10-29 17:35:55 -06:00 |
|
tangxifan
|
c2c384e24b
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[Doc] update documentation about memory bank definition
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2020-10-29 17:04:25 -06:00 |
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tangxifan
|
1ad591c08c
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[Test] Add smart fast configuration test cases for multi-region memory banks to CI
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2020-10-29 16:33:54 -06:00 |
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tangxifan
|
153b265a6d
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[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
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2020-10-29 16:32:05 -06:00 |