bdc13e491e
[arch] adding openfpga arch for ecb
2024-05-20 12:04:52 -07:00
c795dd2f1a
[arch] adding a new arch where feedback loops are modelled by direct connections
2024-05-20 12:00:39 -07:00
65a8db4f38
[arch] replace out-of-date keywords
2024-05-20 11:18:46 -07:00
372e386330
[test] add new tests to verify rr graph preloading in two file formats
2024-05-09 23:10:45 -07:00
b8b8fb6d3b
[test] update golden files
2024-05-07 13:25:23 -07:00
81730da7b2
[test] update golden files
2024-05-07 13:25:04 -07:00
e72d71fe28
[test] update golden outputs
2024-05-07 13:24:45 -07:00
deee75f828
[test] use a different W to avoid vvp collapse
2024-05-07 12:20:58 -07:00
7a0cd764d3
[test] fixed some bugs
2024-05-07 11:23:33 -07:00
13f8dd096e
[test] create a new example script for fixed routing W case
2024-05-07 10:24:15 -07:00
00f39d55ab
[test] now use fixed routing channel width
2024-05-06 23:32:27 -07:00
3615bdceeb
[test] avoid no-fanin errors for hetero arch
2024-05-06 15:32:27 -07:00
10470b311d
[test] now use latest python3 of ubuntu 22.04
2024-05-06 11:44:45 -07:00
c334a0a792
[test] fixed a bug and add golden outputs
2024-05-02 22:07:22 -07:00
98006608c2
[test] add fabric hierarchy file to golden outputs
2024-05-02 22:03:23 -07:00
4e3bbbe45e
[test] add options to write fabric hierarchy file
2024-05-02 22:00:47 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
1af8a4ae4f
[test] add golden outputs
2024-04-11 15:20:34 -07:00
9b0a491819
[test] now validate no time stamp file for fabric pin physical location
2024-04-11 15:16:34 -07:00
d51832a4e2
[ci] typo
2024-04-11 15:13:20 -07:00
e85df6dcfd
[ci] deploy new tests to basic reg tests
2024-04-11 15:11:41 -07:00
20ba0e1dd5
[test] add new testcases to validate options of write_fabric_pin_physical_location
2024-04-11 15:06:50 -07:00
0c680ec426
[test] now test regex as module name for fabric pin physical location
2024-04-11 15:01:19 -07:00
4dedee4011
[test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command
2024-04-11 12:59:13 -07:00
c63cee458b
[script] adapt code format for python
2024-04-10 12:58:05 -07:00
3824b006cc
[test] add new golden outputs
2024-03-29 12:06:00 -07:00
f0639b4567
[test] add new testcase to basic reg test
2024-03-29 11:56:11 -07:00
20386945bd
[test] add a new testcase to validate dump waveform
2024-03-29 11:53:55 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
2bd60dad11
[script] now timing extraction focus on the last found results
2023-12-12 14:10:13 -08:00
592e2e310c
[script] typo
2023-12-12 13:45:23 -08:00
b182b47d0b
[test] use a timing-focus tool path for a testcase
2023-12-12 13:28:35 -08:00
c5cc05a9f5
[script] add a new example default tool path config with a focus on timing
2023-12-12 13:22:50 -08:00
f689ef7654
[script] format
2023-12-12 13:15:03 -08:00
4c0f6e2273
[script] syntax
2023-12-12 13:14:47 -08:00
e753e6d22c
[script] syntax
2023-12-12 13:13:51 -08:00
d9db78ac30
[script] now run fpga task has a new option ``default_tool_path``
2023-12-12 13:11:48 -08:00
1a4aaaf759
[script] update openfpga flow to support args for default tool path
2023-12-12 10:00:50 -08:00
a7b22163a8
[script] fixe the mismatch on keywords against latest vpr
2023-12-12 09:52:42 -08:00
5c839c1858
[test] debug
2023-12-08 13:52:52 -08:00
6a5df804b9
[test] add new testcase to reg test
2023-12-08 13:46:54 -08:00
99f1c5493c
[test] add a new testcase to support vcs
2023-12-08 13:45:23 -08:00
a1169beaf0
Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:34:49 -08:00
7475a002b6
Update repack_design_constraints.xml by changing the separater between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:33:55 -08:00
6055a42196
add test case
2023-12-01 03:04:32 -08:00
dff03e7993
[test] enable missing options in the arch used by benchmark sweeping tests
2023-11-14 09:45:02 -08:00
0b473e3454
[test] fixed the bug in single-mode lut testcase
2023-11-14 09:35:26 -08:00
d108284105
[test] update arch to keep golden outputs
2023-11-14 09:31:07 -08:00
913434b70d
[test] fixed the bug that golden netlists are modified
2023-11-14 09:28:57 -08:00
59d086a27f
[test] try to keep the golden inputs
2023-11-14 09:25:45 -08:00
tangxifan
chungshien
Yitian4Debug
ubuntu