Commit Graph

1676 Commits

Author SHA1 Message Date
tangxifan 1b8748abb4 [core] update vtr 2023-11-13 14:21:34 -08:00
tangxifan d78f18d235 [test] add new testcase 2023-11-13 14:11:34 -08:00
tangxifan 8e875f3453 [test] add a new test case to validate the new feature 2023-11-02 21:08:36 -07:00
tangxifan c6f33bcd7f [test] add new tests to cover the new features 2023-10-06 18:41:57 -07:00
tangxifan 7d83fc914c [core] ad a new test case 2023-10-06 18:31:54 -07:00
tangxifan 5aa206e616 [core] fixed some bugs 2023-09-25 22:27:24 -07:00
tangxifan 60b8c396dc [test] add a new test 2023-09-25 21:25:21 -07:00
tangxifan a4f53c64c6 [test] fixed a bug 2023-09-25 19:28:19 -07:00
tangxifan 663c9c9fa1 [test] add a new test to validate the tile port merge feature 2023-09-25 18:34:34 -07:00
tangxifan a1ed277a88 [test] typo 2023-09-23 15:12:02 -07:00
tangxifan 00e1a5df11 [test] fixed some bugs 2023-09-23 12:44:47 -07:00
tangxifan 195aa7a9a8 [test] developing new test to increase coverage on module renaming 2023-09-23 12:40:20 -07:00
tangxifan f3279bd885 [test] now use 4x4 fabric to check the using index netlists 2023-09-20 22:49:47 -07:00
tangxifan eeb1bd6662 [core] fixed some bugs 2023-09-17 23:16:15 -07:00
tangxifan 3fd60a165d [test] typo 2023-09-17 17:42:15 -07:00
tangxifan 11e976ec92 [test] add a new test to validate renaming on fpga top/core modules 2023-09-17 17:38:37 -07:00
tangxifan 0ef1e0bde5 [test] add a new test to validate renaming rules 2023-09-17 13:29:12 -07:00
tangxifan 559fa45d89 [test] add a new test to validate module renaming using index 2023-09-16 17:55:52 -07:00
tangxifan 1287097ce5 [test] update golden netlists 2023-09-06 22:51:38 -07:00
tangxifan 401f8098a6 [test] update golden copies 2023-09-06 17:35:03 -07:00
tangxifan db0bb291c2 [test] update settings 2023-08-22 15:22:48 -07:00
tangxifan 56cedf6c8b [test] added a new test case to validate the support on different wire segment distribution on X and Y 2023-08-22 11:20:14 -07:00
tangxifan 1b132fd667 [test] add a new testcase to validate the support on different routing channel width on X and Y 2023-08-22 11:06:12 -07:00
tangxifan 15a8d8a76a [test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation 2023-08-18 21:59:06 -07:00
tangxifan 5f6050d404 [test] add a new test to validate combo: group tile, tile annotation and subtile 2023-08-18 21:48:40 -07:00
tangxifan e4c5265b68 [test] arch syntax 2023-08-18 21:40:56 -07:00
tangxifan 5ac8919ce0 [test] add a new testcase to validate subtile with tile annotations 2023-08-18 21:37:15 -07:00
tangxifan f69520d0c3 [arch] format 2023-08-18 11:15:25 -07:00
tangxifan 170a49c34f [test] fix a bug in arch file 2023-08-18 11:15:05 -07:00
tangxifan e82e4f487e [test] add a new test to validate io subtile support 2023-08-18 11:13:34 -07:00
tangxifan 4afd48d930 [test] format 2023-08-17 15:33:09 -07:00
tangxifan 463897f78e [test] fixed a bug in arch 2023-08-17 15:28:59 -07:00
tangxifan 3ac3eb4624 [test] adding more flavor to the L shape 2023-08-17 15:08:27 -07:00
tangxifan 913c232556 [test] deploy new test to basic reg test 2023-08-17 14:54:24 -07:00
tangxifan 85bc890009 [test] add a new test to validate comb options of group tile, group config block and L shape fabric 2023-08-17 14:52:30 -07:00
tangxifan 2f49c25f09 [test] updated 2023-08-11 21:19:06 -07:00
tangxifan b155e660ee [test] fixed a bug 2023-08-11 16:55:35 -07:00
tangxifan 16f102f4c1 [test] deploy new tests to basic regression tests 2023-08-11 13:07:41 -07:00
tangxifan 253d5fa26c [core] a new test to validate the L shape in homo geneous fpga 2023-08-11 13:05:46 -07:00
tangxifan dc0eec8b81 [test] added a new test to validate L shapre 2023-08-11 12:49:38 -07:00
tangxifan 0e9cf6e909 [test] added a new testcase to validate heterogeneous fpga using group config block 2023-08-06 22:11:38 -07:00
tangxifan 3e33f262bc [test] added a new test to validate group_config_block support when fpga_core wrapper is enabled 2023-08-06 18:59:24 -07:00
tangxifan 46b1de08c6 [test] fixed a bug 2023-08-05 22:07:46 -07:00
tangxifan b7048d3dc8 [test] adding new tests to validate group config block 2023-08-03 22:30:41 -07:00
tangxifan 667c5f8944 [test] fixed a bug on the testcase 2023-07-27 22:02:28 -07:00
tangxifan 952e84fce1 [test] now heterogeneous testcases for tile modules pass 2023-07-27 20:30:32 -07:00
tangxifan beaa687a20 [core] fixed bugs on supporting heterogeneous blocks in tile modules 2023-07-27 20:29:18 -07:00
tangxifan 3d56bd0ff2 [test] deploy the new test to ci 2023-07-27 17:03:55 -07:00
tangxifan 65995d7c13 [test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules 2023-07-27 17:03:02 -07:00
tangxifan 46e58a56cb [test] added a new test case to validate clock network when using the tile modules 2023-07-27 16:39:48 -07:00
tangxifan 81d699a723 [test] added a new testcase to validate carry chain connections in tile modules 2023-07-27 16:18:30 -07:00
tangxifan e9f2adf3f9 [test] add a new testcase to validate carry chain connections when using tile modules 2023-07-27 16:06:43 -07:00
tangxifan 1ea8a33d4b [test] add a new testcase to validate global tile connections on tile modules 2023-07-27 15:57:38 -07:00
tangxifan a2848940df [test] add a new testcase to ease debugging 2023-07-26 22:32:03 -07:00
tangxifan 5685fbd5e8 [test] adding a new test case to validate the tile modules on 4x4 fabric 2023-07-26 22:17:39 -07:00
tangxifan bb837f4f79 [test] update golden netlists 2023-07-25 23:39:59 -07:00
tangxifan 0db4ef62e8 [test] add a new test for tile-based fabric: using preconfig testbenches 2023-07-25 15:48:14 -07:00
tangxifan 523cf83cc9 [test] disable pnr writer in test cases 2023-07-25 15:39:25 -07:00
tangxifan 82fe63297a [test] add a new test for top-left tile grouping 2023-07-19 11:22:36 -07:00
tangxifan 930d98f2af [test] deploy new tests 2023-07-08 21:52:16 -07:00
tangxifan 124514c80e [test] update fabric key to new syntax 2023-07-08 18:26:05 -07:00
tangxifan 51e1547634 [test] hotfix 2023-06-26 15:32:16 -07:00
tangxifan 270d6f933b [test] add a new testcase to validate mock wrapper 2023-06-26 15:26:50 -07:00
tangxifan 919d6d8608 [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
tangxifan 523e338d53 [test] debugging 2023-06-23 14:49:52 -07:00
tangxifan 962ba67e36 [test] adding new tests to validate fpga core wrapper naming rules 2023-06-23 14:47:21 -07:00
tangxifan 84edd41342 [test] fixed the bug in adder mapping 2023-06-20 17:09:31 -07:00
tangxifan dba48fb171 [test] reworking adder mapping flow to validate carry chain mapping 2023-06-20 16:57:08 -07:00
tangxifan fd8f371d85 [test] add missing file 2023-06-19 16:44:11 -07:00
tangxifan efc9bf9907 [test] added new test case to validate bitstream generation 2023-06-19 12:40:37 -07:00
tangxifan 97b089ae3c [test] added new testcases to validate fpga core wrapper 2023-06-18 21:01:37 -07:00
tangxifan 1ef8eed589 [test] update no time stamp golden outputs 2023-06-08 15:38:15 -07:00
tangxifan ac31a20376 [test] now bypass clock routing in default example 2023-06-08 13:44:22 -07:00
tangxifan 31b16ba9d7 [test] fixed a few bugs 2023-05-27 12:47:57 -07:00
tangxifan 27b8007d1b [test] rework pcf support testcase for mock wrapper 2023-05-27 12:45:29 -07:00
tangxifan b3471f2703 [test] swap test name 2023-05-27 12:34:10 -07:00
tangxifan 89f184e779 [test] fixed a few bugs 2023-05-27 12:19:28 -07:00
tangxifan b6c90eb99a [core] fixed several bugs which causes bgf and pcf support in mock wrapper failed 2023-05-27 12:13:16 -07:00
tangxifan e1feebc96d [core] fixing bugs on pcf and bgf support for mock efpga wrapper 2023-05-26 21:54:08 -07:00
tangxifan 205e9aa67b [test] add a new test case 2023-05-26 20:55:52 -07:00
tangxifan 77be053966 [test] mock wrapper does not need bitstream forcing 2023-05-26 18:50:54 -07:00
tangxifan 7fbe567d4c [test] add more testcases 2023-05-25 20:24:02 -07:00
tangxifan 812553e13d [test] adding more test cases 2023-05-25 20:17:23 -07:00
tangxifan 11832ad22c [test] add a new testcase to validate mock wrapper 2023-05-25 20:02:10 -07:00
tangxifan 7da7d03db5 [script] add example script for mock wrapper 2023-05-25 19:59:14 -07:00
tangxifan f89b7a82cf [arch] fixed a bug where the array size mismatch the layout name 2023-05-03 22:23:20 +08:00
tangxifan 8d02a6e600 [test] now testcases are using proper arch 2023-05-03 21:47:21 +08:00
tangxifan df771cb33a [test] add a new testcase for subtile and deploy it to basic regression test 2023-05-03 15:41:29 +08:00
tangxifan a3f2ae3c33 [arch] format 2023-05-03 15:23:47 +08:00
tangxifan 02a5057449 [arch] add openfpga arch example using subtile; updated documentation 2023-05-03 15:20:49 +08:00
tangxifan 68f2d9fe5e [arch] add new example arch using subtile in I/O blocks; Updated documentation 2023-05-03 15:16:39 +08:00
tangxifan f06248a1b0 [test] add a new testcase to validate the ccff v2 2023-04-24 14:55:22 +08:00
tangxifan 02e964b16f [test] add a new test case for ccffv2 2023-04-22 15:41:19 +08:00
tangxifan 087636cefa [test] deploy new test to regression tests 2023-04-20 15:06:47 +08:00
tangxifan 40598d25a3 [core] fixed a bug which causes multi-clock programmable network failed in routing 2023-04-20 15:05:45 +08:00
tangxifan fba0a83679 [test] debugging 2-clock network 2023-04-20 14:44:01 +08:00
tangxifan 02b02d18a5 [test] fixed a bug in clock arch 2023-04-20 11:35:36 +08:00
tangxifan b242fd97d6 [test] adding new arch and testcase for 2-clock network 2023-04-20 11:31:49 +08:00
tangxifan 03cb664049 [test] now clock network example script supports multiple clocks 2023-04-20 10:56:36 +08:00
tangxifan 7d333b3669 [test] add a new test for clock network: validate full testbench is working 2023-04-20 10:36:08 +08:00