tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
|
f1ce816d6c
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[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
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tangxifan
|
e850dd5314
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[Tool] Relax checking codes for embedded I/O circuit models
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2020-11-02 13:54:31 -07:00 |
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tangxifan
|
b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
|
1e70825383
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[OpenFPGA Tool] Add XML syntax for configurable regions
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2020-09-28 13:51:43 -06:00 |
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tangxifan
|
052b8b71c7
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[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
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2020-09-27 20:54:58 -06:00 |
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tangxifan
|
491433fae2
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[OpenFPGA Tool] Update XML parser for fabric regions
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2020-09-27 20:41:01 -06:00 |
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tangxifan
|
48b2bff0d9
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[OpenFPGA Tool] Update fabric key data structure to support regions
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2020-09-27 20:08:11 -06:00 |
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tangxifan
|
94047037c5
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[OpenFPGA Tool] Streamline codes in openfpga arch parser
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2020-09-27 14:33:14 -06:00 |
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tangxifan
|
51d96244c6
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[OpenFPGA Tool] Remove deprecated XML syntax
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2020-09-26 14:30:57 -06:00 |
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tangxifan
|
8b8ce22fd1
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[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
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2020-09-23 20:37:28 -06:00 |
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tangxifan
|
064678fe32
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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tangxifan
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f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
|
8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
|
c23742c751
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 20:13:27 -06:00 |
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tangxifan
|
fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
|
c31d36deb6
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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
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2020-09-14 16:16:03 -06:00 |
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tangxifan
|
9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
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2020-08-23 14:06:03 -06:00 |
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tangxifan
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b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
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161d660837
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update documentation for the initial offset when mapping physical pins
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2020-08-19 15:00:46 -06:00 |
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tangxifan
|
3eea12ceae
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added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
|
2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
|
35af0dd676
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streamline fabric bitstream file format
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2020-07-27 16:34:43 -06:00 |
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tangxifan
|
92d2d2d849
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add fabric bitstream XML writer
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2020-07-26 21:00:57 -06:00 |
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tangxifan
|
a3d22c56e3
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bug fix in FPGA-SPICE
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2020-07-24 19:51:32 -06:00 |
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tangxifan
|
6d046efc52
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add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
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2020-07-24 16:25:27 -06:00 |
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tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
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tangxifan
|
de4586217f
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now device binding is not mandatory for circuit models
|
2020-07-14 12:04:22 -06:00 |
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tangxifan
|
e2b492f184
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add circuit model tech binding
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2020-07-13 20:35:10 -06:00 |
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tangxifan
|
62fd0947f5
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using a unified string to replace multi net names to save memory of bitstream database
|
2020-07-08 16:28:20 -06:00 |
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tangxifan
|
824b56f14c
|
fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
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tangxifan
|
1ad6e8292a
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move constants from verilog domain to common so that FPGA-SPICE can share
|
2020-07-05 11:39:46 -06:00 |
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tangxifan
|
2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
|
70d9678578
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reserve child block in bistream manager
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2020-07-03 14:04:10 -06:00 |
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tangxifan
|
7d9c36aae1
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use length instead of msb in bitstream manager for block bits to save memory
|
2020-07-03 12:06:15 -06:00 |
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tangxifan
|
2783fda344
|
use index range instead of vector for block bitstream
|
2020-07-03 11:42:38 -06:00 |
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tangxifan
|
6ea857ae6c
|
use fast method to inquire number of bits and blocks in bitstream databases
|
2020-07-03 10:55:25 -06:00 |
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tangxifan
|
6397cbe9d2
|
remove unused data in bitstream manager to compact memory usage
|
2020-07-03 10:35:35 -06:00 |
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tangxifan
|
246b4d5ac6
|
reserve block bits to save memory
|
2020-07-02 21:52:32 -06:00 |
|
tangxifan
|
043fb54206
|
remove unused data in bitstream database
|
2020-07-02 20:53:18 -06:00 |
|
tangxifan
|
9799fea48f
|
optimizing bitstream storage
|
2020-07-02 19:33:53 -06:00 |
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tangxifan
|
dee4be96af
|
reserve all the input/output net storage in bitstream manager
|
2020-07-02 19:17:34 -06:00 |
|
tangxifan
|
f97e3bfba6
|
add timer to openfpga shell
|
2020-07-02 18:02:33 -06:00 |
|
tangxifan
|
e82d0d9f34
|
drop id list in bitstream manager to save memory usage
|
2020-07-02 16:18:32 -06:00 |
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tangxifan
|
9f19c36a89
|
use char in fabric bitstream to save memory footprint
|
2020-07-02 15:56:50 -06:00 |
|
tangxifan
|
405824081b
|
reserve configuration blocks and bits in bitstream manager builder to be memory efficient
|
2020-07-02 15:28:52 -06:00 |
|
tangxifan
|
9d32a5b81f
|
add alias name support for fabric key
|
2020-06-27 14:59:53 -06:00 |
|
tangxifan
|
b36da17a08
|
bug fix for directory creation when the input is an empty string
|
2020-06-25 10:34:34 -06:00 |
|
tangxifan
|
e2d3ac78ec
|
skip empty lines in OpenFPGA shell
|
2020-06-25 10:18:05 -06:00 |
|
tangxifan
|
aded675633
|
rename files in fpga bitstream library to be consistent with conventions
|
2020-06-21 13:06:39 -06:00 |