tangxifan
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afde3eaa65
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Update patch_updater.yml
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2022-09-21 21:29:52 -07:00 |
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tangxifan
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d7fb6d9547
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Merge pull request #747 from lnis-uofu/vtr_upgrade
Now use latest VTR as a submodule
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2022-09-21 21:25:07 -07:00 |
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tangxifan
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8ee3fb879f
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Update VERSION.md
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2022-09-21 21:16:20 -07:00 |
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tangxifan
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d543a8661f
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Merge branch 'master' into vtr_upgrade
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2022-09-21 19:08:50 -07:00 |
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tangxifan
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88cffb4b39
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Merge pull request #802 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-09-21 17:06:26 -07:00 |
github-actions[bot]
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62e91c1dab
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Updated Patch Count
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2022-09-22 00:03:28 +00:00 |
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tangxifan
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79b260f5e1
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[arch] update missing arch
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2022-09-21 16:52:32 -07:00 |
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tangxifan
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b1f8cdab3c
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[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
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2022-09-21 15:28:56 -07:00 |
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tangxifan
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eaa0b5588a
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[test] fixed a bug in pin constrain examples
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2022-09-21 14:10:12 -07:00 |
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tangxifan
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b532bca9d2
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[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
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2022-09-21 10:54:16 -07:00 |
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tangxifan
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baac236ed7
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[test] fixed a bug in example scripts due to the changes on vpr options
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2022-09-21 10:52:49 -07:00 |
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tangxifan
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d0b018ad6e
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[script] mismatches in vpr options due to upgrade
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2022-09-21 09:27:26 -07:00 |
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tangxifan
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40edf859e3
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Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-20 22:38:06 -07:00 |
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tangxifan
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97f0445787
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[arch] upgrade arch file which was designed for v1.1
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2022-09-20 22:37:35 -07:00 |
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tangxifan
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36603f9772
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Merge branch 'master' into vtr_upgrade
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2022-09-20 21:08:06 -07:00 |
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tangxifan
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1354a4bfa8
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Merge pull request #800 from lnis-uofu/reg_hotfix
[test] Now git diff in basic regression tests should capture the changes on golden outputs
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2022-09-20 20:53:47 -07:00 |
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tangxifan
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e0f632cc9c
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[test] fixed a bug
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2022-09-20 20:29:34 -07:00 |
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tangxifan
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645d8df7b9
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[test] fixed a bug
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2022-09-20 20:09:41 -07:00 |
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tangxifan
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9042fc2422
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[test] now reg test should show diff details when failed
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2022-09-20 19:32:34 -07:00 |
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tangxifan
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b8f1520367
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[test] fixed a bug
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2022-09-20 18:12:23 -07:00 |
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tangxifan
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4e254a304d
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[test] now golden netlists have no relationship with OPENFPGA_PATH
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2022-09-20 18:10:52 -07:00 |
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tangxifan
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5e23be19a5
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[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
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2022-09-20 18:07:31 -07:00 |
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tangxifan
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1b0b50b928
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[test] update golden netlist
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2022-09-20 16:04:05 -07:00 |
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tangxifan
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a137f7148c
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[arch] fixed a bug
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2022-09-20 15:47:15 -07:00 |
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tangxifan
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da157ed5de
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[test] debugging git-diff
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2022-09-20 15:31:39 -07:00 |
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tangxifan
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3f8106f12e
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[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
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2022-09-20 15:19:32 -07:00 |
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tangxifan
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b630d60b7e
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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
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2022-09-20 14:14:18 -07:00 |
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tangxifan
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6a896a9845
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[test] debugging
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2022-09-20 14:08:22 -07:00 |
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tangxifan
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ecfdc4a83a
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[test] debugging
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2022-09-20 13:51:32 -07:00 |
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tangxifan
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abee802830
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[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
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2022-09-20 13:46:30 -07:00 |
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tangxifan
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bdcdc7d294
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[test] Now git diff in basic regression tests should capture the changes on golden outputs
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2022-09-20 13:36:31 -07:00 |
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tangxifan
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37c5056d6a
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[test] now use a fixed routing channel width for quicklogic tests
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2022-09-20 12:25:40 -07:00 |
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tangxifan
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846ca26311
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[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
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2022-09-20 12:08:24 -07:00 |
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tangxifan
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b3449a338f
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[arch] update out-of-date vpr arch from v1.1 to v1.2
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2022-09-20 09:51:43 -07:00 |
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tangxifan
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63cb8d589d
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[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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tangxifan
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40663f956c
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[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
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2022-09-19 21:55:15 -07:00 |
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tangxifan
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d9bd0a6cf3
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[test] disable clustering-routing result sync-up when calling vpr in example scripts
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2022-09-19 20:52:04 -07:00 |
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tangxifan
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fca1c82388
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[test] disable clustering and routing sync when using VPR
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2022-09-19 20:33:35 -07:00 |
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tangxifan
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e19ca1c6d1
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[engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb
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2022-09-19 18:49:54 -07:00 |
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tangxifan
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1177e8740e
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[engine] update vtr
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2022-09-19 15:35:23 -07:00 |
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tangxifan
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9b0a97d391
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[engine] update vtr
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2022-09-19 15:05:45 -07:00 |
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tangxifan
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c922259c23
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[engine] remove warnings and update vtr
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2022-09-19 14:53:30 -07:00 |
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tangxifan
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90ddd2ce32
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[engine] now get incoming edges for IPINs only from GSB
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2022-09-19 14:02:13 -07:00 |
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tangxifan
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5eba2d7f6f
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[engine] update vpr
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2022-09-19 13:31:08 -07:00 |
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tangxifan
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050b6edcba
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[engine] update vtr
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2022-09-19 13:23:14 -07:00 |
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tangxifan
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3c6ef1925c
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[engine] now sort ipin incoming edges
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2022-09-19 11:00:08 -07:00 |
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tangxifan
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87c63d1437
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[engine] update vtr
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2022-09-19 10:20:19 -07:00 |
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tangxifan
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c340330ae0
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[engine] update vtr
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2022-09-19 09:54:57 -07:00 |
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tangxifan
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a7416d285f
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[engine] update vpr
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2022-09-18 22:14:12 -07:00 |
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tangxifan
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fec6905c20
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[engine] update vtr
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2022-09-18 21:57:22 -07:00 |