taoli4rs
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347a29f27c
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Fix test name in basic regression test script.
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2022-07-20 21:05:31 -07:00 |
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taoli4rs
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cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
tangxifan
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9832722056
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[test] now add QuickLogic memory bank to fpga bitstream regression tests
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2022-05-25 11:42:32 +08:00 |
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tangxifan
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86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
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2022-05-25 11:19:49 +08:00 |
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tangxifan
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7d694acf32
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[test] debugging basic reg test paths
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2022-05-23 11:21:36 +08:00 |
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tangxifan
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b41cbad5d3
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[test] force to run git diff under root directory
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2022-05-23 10:32:43 +08:00 |
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tangxifan
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488a934097
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[test] give abs path for git diff in basic regression tests
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2022-05-23 09:12:33 +08:00 |
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tangxifan
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0dc7caf3b7
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[test] now regression test script supports remove all run dir through command-line options
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2022-05-22 13:15:39 +08:00 |
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tangxifan
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751d87b8e3
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[test] fix a bug in detect changes in golden netlists
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2022-05-22 13:06:47 +08:00 |
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tangxifan
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d7e854eae7
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[test] deploy new test to ci
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2022-05-09 17:23:57 +08:00 |
Ganesh Gore
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522982c9ba
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Adde vtr_benchmarks_template for demo
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2022-05-06 22:40:36 -06:00 |
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Ganesh Gore
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1e243650b9
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Added option to copy example projects
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2022-05-03 14:06:16 -06:00 |
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Ganesh Gore
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21c3dbf611
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Added regression for template project
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2022-05-02 23:23:45 -06:00 |
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tangxifan
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9bd66d531e
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[Test] Deploy the new test case to basic regression tests
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2022-04-13 16:06:27 +08:00 |
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tangxifan
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3e3a65223c
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[Test] Deploy new test case to basic regression tests
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2022-03-20 11:04:07 +08:00 |
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tangxifan
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a615c9d4e3
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[Test] Rename test cases
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2022-02-24 09:43:41 -08:00 |
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tangxifan
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b27a04eb24
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[Test] Now test case has a config done CCFF
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2022-02-23 22:07:11 -08:00 |
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tangxifan
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cf31879b20
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[Test] Deploy new test to basic regression tests
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2022-02-23 16:03:56 -08:00 |
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tangxifan
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68644ea0f6
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[Test] Add the new test to basic regression tests
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2022-02-18 15:44:07 -08:00 |
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tangxifan
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fe9e0ff977
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[Test] Add the new test to basic regression tests
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2022-02-18 15:38:53 -08:00 |
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tangxifan
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85c893c94c
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[Test] Add new test to basic regression tests
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2022-02-18 15:30:08 -08:00 |
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tangxifan
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43d852d8a1
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[Test] Add the bus group test case to basic regression tests
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2022-02-18 12:27:25 -08:00 |
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tangxifan
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d667102a43
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[Test] Add new test case to regression tests
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2022-02-14 15:58:53 -08:00 |
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tangxifan
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0268814fc6
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[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
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2022-02-14 12:20:56 -08:00 |
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tangxifan
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27ac2fafe5
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[Test] Add the new test case to regression tests
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2022-02-01 13:45:46 -08:00 |
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tangxifan
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9871fe88fb
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[Test] Typo fix
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2022-01-31 13:03:45 -08:00 |
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tangxifan
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da8fc0f5d4
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[Test] Add a new test case to validate ``--use_relative_path``
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2022-01-31 13:02:19 -08:00 |
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tangxifan
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a9042318cf
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[Test] Deploy the test case to regression tests
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2022-01-26 11:26:17 -08:00 |
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tangxifan
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11e045992d
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[Test] Now only compare on the golden netlist changes to branch
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2022-01-25 21:24:10 -08:00 |
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tangxifan
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c2c827ee10
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[Script] Fix a bug in git-diff for regression tests
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2022-01-25 20:27:41 -08:00 |
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tangxifan
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fedb1bd2e3
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[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
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2022-01-25 16:41:36 -08:00 |
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tangxifan
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5c0f63ddd9
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[Test] Update regression tests for the new test about ``--no_time_stamp``
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2022-01-25 16:30:48 -08:00 |
Aram Kostanyan
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397f2e71f1
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Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
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2022-01-19 20:43:26 +05:00 |
Awais Abbas
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469b3a960c
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basic reg test updated
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2022-01-14 15:44:26 +05:00 |
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Awais Abbas
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793e40cb95
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basic_reg test for yosys-only flow added in OpenFPGA regression test scripts
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2022-01-14 15:39:26 +05:00 |
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tangxifan
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628191da5f
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[Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests
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2022-01-02 20:21:58 -08:00 |
nadeemyaseen-rs
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236910cde4
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-12-09 00:00:21 +05:00 |
coolbreeze413
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b86bd1ca68
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re-enable counter_5clock,sdc_controller, lut_adder tests
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2021-11-19 18:06:06 +05:30 |
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nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
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coolbreeze413
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840fa399c6
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enable single counter test (fails, needs debug)
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2021-11-09 21:36:33 +05:30 |
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Aram Kostanyan
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a707226ba6
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Added 'basic_tests/verific_test' test case into regression tests suite.
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2021-11-01 18:33:33 +05:00 |
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tangxifan
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ff264c00a2
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-31 11:51:34 -07:00 |
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tangxifan
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18bab18032
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[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
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2021-10-30 13:20:58 -07:00 |
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tangxifan
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2bf203cd00
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[Test] Deploy the new test to basic regression test
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2021-10-11 09:54:39 -07:00 |
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tangxifan
|
982a324e0d
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[Test] Temporarily disable some tests; Will go back later
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2021-10-10 23:30:50 -07:00 |
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tangxifan
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8f9e564cd5
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[Test] Add the new test to basic regression test
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2021-10-09 20:45:23 -07:00 |
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tangxifan
|
554018449e
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[Test] Update regression test script
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2021-10-06 12:10:37 -07:00 |
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tangxifan
|
064ac478f3
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[Test] Deploy news test to fpga-bitstream regression tests
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2021-10-05 19:01:03 -07:00 |
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tangxifan
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b21f212031
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[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
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2021-10-05 11:39:53 -07:00 |
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tangxifan
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492db50efe
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[Test] Deploy the new test to basic regression tests
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2021-10-05 10:59:26 -07:00 |