tangxifan
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fc154b8560
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[Architecture] Bug fix due to switching CCFF cell
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2020-09-24 16:45:56 -06:00 |
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tangxifan
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79875d5a91
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[Architecture] Bug fix in the configuration chain arch using both reset and set
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2020-09-24 15:27:26 -06:00 |
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tangxifan
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9cb67e6097
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[Architecture] Now all the configuration chain architecture use the DFFR cell by default
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2020-09-24 15:19:37 -06:00 |
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tangxifan
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178afb3c7f
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[Architecture] Add configuration chain architectures using different DFF cells
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2020-09-24 14:23:27 -06:00 |
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tangxifan
|
98d88dc686
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[Architecture] Bug fix for vanilla memory organization
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2020-09-24 14:13:48 -06:00 |
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tangxifan
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539bb617f9
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[Architecture] Add reset test case for frame based configuration
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2020-09-24 12:17:18 -06:00 |
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tangxifan
|
2add0406a7
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[Architecture] Update architecture files for new latch naming
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2020-09-24 12:14:03 -06:00 |
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tangxifan
|
83971bba41
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[Architecture] Update cell ports for native SRAM cell
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2020-09-24 10:31:31 -06:00 |
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tangxifan
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56c9aab190
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[Architecture] Add architecture to use different SRAM cells for memory bank
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2020-09-24 10:15:08 -06:00 |
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tangxifan
|
10b6e1dc0d
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[Architecture] bug fix for active-low
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2020-09-23 23:06:46 -06:00 |
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tangxifan
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5d60b4ef8c
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[Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set
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2020-09-23 23:02:49 -06:00 |
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tangxifan
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8e780635df
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[Regression Test] Rename test case in CI
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2020-09-23 22:59:46 -06:00 |
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tangxifan
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c7fc0178b0
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[Architecture] Rename to be consist with other architectures
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2020-09-23 22:57:06 -06:00 |
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tangxifan
|
707300a6e4
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[Architecture] Bug fix for using both reset and set architecture
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2020-09-23 22:07:40 -06:00 |
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tangxifan
|
77a1f99564
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[Architecture] Bug fix for architecture using set only
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2020-09-23 22:04:24 -06:00 |
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tangxifan
|
9331ef941d
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[Architecture] Add architecture that use both set and reset signals
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2020-09-23 21:46:04 -06:00 |
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tangxifan
|
7591060fbd
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[Architecture] Add configurable latch Verilog designs and assoicated architectures
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2020-09-23 21:45:06 -06:00 |
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tangxifan
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8fa4fa1125
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[Architecture] Add openfpga architecture using set signals for configurable latch
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2020-09-23 21:39:31 -06:00 |
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tangxifan
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2869eae8a9
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[Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol
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2020-09-23 20:43:15 -06:00 |
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tangxifan
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fc60b18191
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[Architecture] Now a regular flip-flop can be used in frame-based configuration
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2020-09-23 20:41:49 -06:00 |
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tangxifan
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8e4e66038a
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[Architecture] Bug fix for standalone memory
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2020-09-23 19:32:48 -06:00 |
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tangxifan
|
1864b080a2
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[Architecture] Bug fix in configurable latch Verilog HDL
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2020-09-23 18:28:45 -06:00 |
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tangxifan
|
ebb866d04a
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[Architecture] Patch frame based using ccff
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2020-09-23 18:04:14 -06:00 |
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tangxifan
|
906191e931
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[Architecture] Use strict latch Verilog HDL in frame-based procotol
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2020-09-23 17:58:13 -06:00 |
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tangxifan
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1a2c66f07d
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[Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell
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2020-09-23 17:34:49 -06:00 |
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tangxifan
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a3c982a83f
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[Architecture] Patch the openfpga architecture using active-low configurable latch
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2020-09-23 17:27:16 -06:00 |
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tangxifan
|
893859be37
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[Architecture] Add openfpga architecture using active-low configurable latch
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2020-09-23 17:21:00 -06:00 |
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tangxifan
|
1aab691e9d
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[Architecture] Add openfpga architecture using pattern based local routing
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2020-09-23 16:06:16 -06:00 |
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tangxifan
|
72749be4bd
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[Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:31:34 -06:00 |
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tangxifan
|
13df6c1c21
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[Architecture] Add openfpga architecture for k4n4 using multiple segments
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2020-09-22 12:36:11 -06:00 |
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tangxifan
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26fba4a94b
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[Architecture] Add openfpga architectue for k4n4 with bram blocks
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2020-09-22 12:22:59 -06:00 |
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tangxifan
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dd192a2f54
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[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
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2020-09-22 11:34:23 -06:00 |
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tangxifan
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60f328a2ab
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[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
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2020-09-21 17:36:57 -06:00 |
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tangxifan
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f5b7ac6269
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[OpenFPGA Architecture] Add a new architecture with no local routing
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2020-09-16 18:04:55 -06:00 |
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tangxifan
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aaf63050bb
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[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
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2020-09-14 15:58:34 -06:00 |
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tangxifan
|
aa9521b23b
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[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
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2020-09-14 15:57:44 -06:00 |
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tangxifan
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eecfd186f0
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[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
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2020-09-14 15:46:10 -06:00 |
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tangxifan
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4b3142c4ee
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[Architecture File] Patch openfpga architecture with default circuit model definition
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2020-08-23 15:13:28 -06:00 |
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tangxifan
|
9101ba1021
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[Architecture Language] Update openfpga architecture files for default models
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2020-08-23 14:55:44 -06:00 |
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tangxifan
|
18735894f9
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bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
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2020-08-19 15:27:30 -06:00 |
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tangxifan
|
aa4a9b28cc
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start testing the initial offset in the flagship architecture
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2020-08-19 15:03:46 -06:00 |
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tangxifan
|
f64079641d
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bug fix in flagship vpr arch with frac mem and dsp
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2020-08-19 12:43:58 -06:00 |
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tangxifan
|
42b5ea2cb1
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bug fix in openfpga arch for frac mem and dsp
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2020-08-18 20:42:36 -06:00 |
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tangxifan
|
098859fe06
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bug fix in the frac memory & DSP architecture
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2020-08-18 15:05:51 -06:00 |
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tangxifan
|
f833e0ec66
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add a flagship architecture using fracturable memory and dsp
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2020-08-17 17:49:51 -06:00 |
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tangxifan
|
fefcd88f14
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update openfpga architecture README for power-gating
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2020-07-22 21:55:59 -06:00 |
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tangxifan
|
22159531c5
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bug fix in power gating support of FPGA-Verilog
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2020-07-22 20:21:38 -06:00 |
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tangxifan
|
87ef7f9f99
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add power gate example architecture
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2020-07-22 20:06:10 -06:00 |
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tangxifan
|
8ade40713a
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add missing architecture for CI
|
2020-07-22 14:07:39 -06:00 |
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tangxifan
|
f754c8af06
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use k6_n10 architecture to reduce CI runtime
|
2020-07-22 13:45:55 -06:00 |