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OpenFPGA
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3,730 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

341 Commits

Author SHA1 Message Date
tangxifan 2baf3ddd2f [Test] Add test cases for 'report_bitstream_distribution' command 2021-05-07 12:06:24 -06:00
tangxifan f1658cb735 [Test] Deploy blinking to test cases 2021-05-06 15:17:45 -06:00
tangxifan a5e40fbb21
Merge branch 'master' into micro_benchmarks 2021-04-28 14:27:58 -06:00
tangxifan b72d4bd807 [Test] Update test case for 1kbit DPRAM architectures 2021-04-28 11:28:53 -06:00
tangxifan 5c729657ef [Test] Bug fix in test case for DPRAM whose width = 2 2021-04-28 10:31:22 -06:00
tangxifan 0bec4b3f32 [Test] Update task configuration to use proper openfpgashell script 2021-04-27 23:34:42 -06:00
tangxifan fdfbdc4613 [Test] Update task configuration files to use dedicated yosys script 2021-04-27 20:05:04 -06:00
tangxifan b8ced5377f [Test] Add a test case for i/o mapping writer 2021-04-27 14:41:15 -06:00
tangxifan 6291871faf [Test] Added a test for the example architecture with 2x2 DSP blocks 2021-04-26 16:28:43 -06:00
tangxifan 80f98328df [Test] Update test settings for architecture with fracturable DSP blocks 2021-04-24 15:16:50 -06:00
tangxifan 1c6b9a23d7 [Test] Add new test for multi-mode 16-bit DSP blocks 2021-04-24 13:29:29 -06:00
tangxifan 189c94ff19 [Test] Deploy new mac benchmarks to tests 2021-04-23 20:44:14 -06:00
tangxifan 784713e88a [Test] Add golden results for IWLS2005 as a simple QoR check 2021-04-22 19:27:31 -06:00
tangxifan 1dcb8e39a9 [Test] Unlock more IWLS'2005 benchmarks in testing 2021-04-22 09:23:33 -06:00
tangxifan 61a473e479 [Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support 2021-04-21 22:56:19 -06:00
tangxifan 3a5c26c6a1 [Test] Update IWLS test by using new architecture and customize DFF techmap 2021-04-21 19:51:25 -06:00
tangxifan 8046b16c15 [Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing 2021-04-21 14:04:34 -06:00
tangxifan 578d81b67a [Test] Patch task configuration file 2021-04-19 16:15:00 -06:00
tangxifan 5976cc0a1c [Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection 2021-04-19 15:54:18 -06:00
tangxifan da95da933b [Test] Add pin constraint file to map reset to correct FPGA pins 2021-04-17 15:04:26 -06:00
tangxifan c020333512
Merge branch 'master' into dff_techmap 2021-04-16 20:54:28 -06:00
tangxifan 7172fc9ea1 [Test] Patch test for architecture using asynchronous DFFs 2021-04-16 20:48:37 -06:00
tangxifan 93be81abe1 [Test] Add test case for architecture using DFF with reset 2021-04-16 20:00:48 -06:00
tangxifan 1566a5558a [Test] Add task configuration file for iwls2005 2021-04-16 16:10:31 -06:00
tangxifan b469705819
Merge branch 'master' into fpga_sdc_test 2021-04-11 21:14:46 -06:00
tangxifan 94c4c817eb [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
tangxifan a4893e27cf [Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification 2021-04-11 17:26:27 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan 8c970a792a [Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier 2021-03-23 15:33:00 -06:00
tangxifan 351dec5935 [Test] Add QoR csv file for vtr benchmarks 2021-03-23 11:15:02 -06:00
tangxifan 61eddb08de [Test] Update task configuration by commenting out high-runtime VTR benchmarks 2021-03-22 14:42:42 -06:00
tangxifan 4bfd0c0a02 [Test] Enable more VTR benchmark in testing 2021-03-22 12:53:30 -06:00
tangxifan cc10b10703 [Test] Enable more benchmarks for testing; See problems when mapping BRAMs 2021-03-20 22:53:37 -06:00
tangxifan 9a3aff274f [Test] Use fix routing channel width to save runtime for VTR benchmarks 2021-03-20 21:59:44 -06:00
tangxifan ca9a70fc88 [Test] Comment out benchmarks have problems in synthesis 2021-03-20 21:29:21 -06:00
tangxifan 125e94a6b3 [Test] Add full VTR benchmark (with most commented); ready for massive testing 2021-03-20 21:01:18 -06:00
tangxifan f3792bc6f6 [Test] Update VTR benchmark test case to include DSP example benchmark 2021-03-20 18:09:19 -06:00
tangxifan 1976a8068f [Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added) 2021-03-17 15:11:17 -06:00
tangxifan e1f8b252b1 Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-16 20:05:21 -06:00
tangxifan d12a8a03fd [Test] Update test case using yosys bram parameters 2021-03-16 19:52:17 -06:00
tangxifan 73b06256d0 [Test] Deploy the new yosys script supporting BRAM to regression tests 2021-03-16 16:52:59 -06:00
tangxifan e61857aa2b
Merge branch 'master' into ganesh_dev 2021-03-11 19:17:02 -07:00
tangxifan 366bec232c [Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI 2021-03-11 15:25:48 -07:00
tangxifan a6186db315 [Test] Update bitstream annotation with new syntax 2021-03-10 20:45:17 -07:00
tangxifan 7d07f5d8cb [Test] Update bitstream setting example with mode bit overwriting 2021-03-10 15:34:53 -07:00
tangxifan d21909ad6c [Test] Use custom rewriting script in lut_adder test 2021-03-10 13:48:20 -07:00
Tarachand Pagarani db8ea86b2f update tests to use no_ff_map and remove tests that need async set/reset for now 2021-03-10 10:04:45 -08:00
Tarachand Pagarani 608bd1f658 comment out desings that utilize local async reset/preset 2021-03-09 19:24:01 -08:00
Tarachand Pagarani 7f4c20ff33 comment out desings that utilize local async reset/preset 2021-03-09 10:37:06 -08:00
Tarachand Pagarani c4b83aeaa9 bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type 2021-03-09 00:46:40 -08:00