AurelienUoU
|
ff9b84d800
|
Bug fix in Icarus requirement
|
2019-05-10 14:07:32 -06:00 |
Baudouin Chauviere
|
79f3db9880
|
removed the now useless tutorial part
|
2018-12-10 13:57:01 -07:00 |
tangxifan
|
72fbd8d6a8
|
update blif reader to identify clock signals
|
2018-12-10 13:28:44 -07:00 |
|
Baudouin Chauviere
|
79930982cf
|
Changed for the naming
|
2018-12-08 16:19:38 -07:00 |
|
tangxifan
|
b3c1018e28
|
fixed a bug in wired LUT
|
2018-12-06 16:50:30 -07:00 |
|
Baudouin Chauviere
|
0b1ccf7722
|
and in the config path as well
|
2018-12-06 14:57:32 -07:00 |
|
Baudouin Chauviere
|
fe47b3d21f
|
Changing arch from memory dec to scff. Get the bitstream from go.sh
|
2018-12-06 14:03:17 -07:00 |
|
tangxifan
|
4f5f8de46f
|
Add Yosys and update flow_flow Perl Script
|
2018-11-30 21:14:43 -07:00 |
|
Baudouin Chauviere
|
d55ecd154b
|
Add the PTM to the benchmark flow
|
2018-11-21 11:32:34 -07:00 |
|
Baudouin Chauviere
|
8ce0a84bc1
|
Correction of the global make, the fpga_flow and the doc
|
2018-11-20 14:47:15 -07:00 |
|
Baudouin Chauviere
|
03e902023a
|
Perl script integrated to flow. rm shell one
|
2018-11-20 13:32:11 -07:00 |
|
Baudouin Chauviere
|
15d69e2bb1
|
Generation script finished TODO: integration in flow
|
2018-11-20 13:24:31 -07:00 |
|
Baudouin Chauviere
|
e74f05a161
|
Switching from sh to pl
|
2018-11-20 10:15:31 -07:00 |
Baudouin Chauviere
|
9611576d6a
|
Update on the examples to respect the new syntax
|
2018-11-19 15:50:29 -07:00 |
|
Baudouin Chauviere
|
dddca8acbb
|
Global Makefile and typo correction
|
2018-10-24 17:34:51 -06:00 |
|
Baudouin Chauviere
|
9538dbd644
|
Config script written and changed some rights for some files
|
2018-10-24 15:59:32 -06:00 |
Aurelien Alacchi
|
e0c2fc2c8a
|
Documentation_code&example_update
|
2018-10-12 15:50:09 -06:00 |
|
Baudouin Chauviere
|
e5c6471fc2
|
Update of the Readme and added an example
ReadMe is now cleaner
|
2018-10-03 17:10:29 -06:00 |
|
Baudouin Chauviere
|
4a4f539365
|
Change rights script
|
2018-09-27 15:51:09 -06:00 |
|
Baudouin Chauviere
|
665678267d
|
Change rights script
|
2018-09-27 15:17:48 -06:00 |
Xifan Tang
|
1cf066d3ad
|
Fixing minor bugs
|
2018-09-06 14:25:23 -06:00 |
|
Xifan Tang
|
c009a37580
|
fix minor bugs
|
2018-09-04 17:56:37 -06:00 |
|
Xifan Tang
|
42da9160f0
|
Clean codes and update
|
2018-09-04 17:49:20 -06:00 |
|
Xifan Tang
|
00ecd0bb1d
|
Cleanup codes and organization
|
2018-09-04 17:31:30 -06:00 |
|
Xifan Tang
|
cb15bb5082
|
Clean code and fix minor bugs
|
2018-08-10 13:46:00 -06:00 |
|
Xifan Tang
|
b0ef554b35
|
Add power property XML
|
2018-08-09 11:27:36 -06:00 |
|
Xifan Tang
|
90669d19c5
|
Update FPGA-SPICE and flow configurations
|
2018-08-09 11:27:16 -06:00 |
|
Xifan Tang
|
fe13168f8f
|
Add ABC and ACE2, fix bugs for fpga_flow and VPR
|
2018-07-27 22:54:52 -06:00 |
|
Xifan Tang
|
158dec405e
|
Reorganize the code directory
|
2018-07-26 11:28:21 -06:00 |