Commit Graph

1329 Commits

Author SHA1 Message Date
tangxifan 59deb97d5d [core] code format 2024-01-12 14:17:10 -08:00
tangxifan f1e3d53da6 [core] fixed a bug where pb pin fixup may fail when subtile capacities are not same 2024-01-12 14:16:07 -08:00
tangxifan bacd845139 [core] code format 2023-12-08 13:41:41 -08:00
tangxifan 5e181cbe72 [core] add a new option for simulator type to verilog full testbench generator 2023-12-08 13:07:25 -08:00
tangxifan 0e945d6e71 [core] fix a bug in ql memory bank tb where VCS failed 2023-12-08 11:36:54 -08:00
Yitian4Debug 8a24b1ba8c
Update repack_option.h
code clean up
2023-12-05 10:17:52 -08:00
Yitian4Debug 94f7b2f4e2
Update repack.cpp
code clean up
2023-12-05 10:16:10 -08:00
Yitian4Debug d2379cfff6
Update repack_option.h 2023-12-05 09:34:34 -08:00
Yitian4Debug 231cb0f89b
Update repack_option.cpp 2023-12-05 09:30:32 -08:00
Yitian4Debug 83fdaea13d
Update repack.cpp 2023-12-05 09:28:27 -08:00
Yitian4Debug 5ca928efda
Merge branch 'master' into repack_debug 2023-12-04 13:21:10 -08:00
chungshien c18f4d7f44 Issue:1466 - Fix WL ordering in bitstream generation 2023-11-29 21:55:53 -08:00
ubuntu d28f024b61 minor change 2023-11-29 01:53:18 -08:00
tangxifan 1aac6681bc
Merge branch 'master' into repack_debug 2023-11-22 10:48:59 -08:00
ubuntu e3682ac955 reformate the code 2023-11-22 01:15:55 -08:00
ubuntu 93d5b850f0 reset the error flag in each parsing iteration 2023-11-22 00:04:51 -08:00
ubuntu 8f9161b438 format the code 2023-11-21 22:28:37 -08:00
ubuntu ee392f1b46 add ignore_net to repackdesign constraint 2023-11-21 21:47:03 -08:00
tangxifan b780f0a552 [core] code format 2023-11-03 14:39:49 -07:00
tangxifan e48de682ed [core] fixed som ebugs 2023-11-03 14:39:28 -07:00
tangxifan b2e1eb30c7 [core] code format 2023-11-03 13:50:04 -07:00
tangxifan 21813eb59f [core] now full testbench uses bitstream in different sizes 2023-11-03 13:48:21 -07:00
tangxifan 2cd3453629 [core] fixed the bug in ccff v2 on config enable signal drivers 2023-11-03 10:25:12 -07:00
tangxifan 8bee65853c [core] add missing files 2023-11-02 19:01:25 -07:00
tangxifan 649d44b2d8 [core] code format 2023-11-02 16:33:55 -07:00
tangxifan 36fa020c15 [core] syntax 2023-11-02 16:33:19 -07:00
tangxifan 75e9e98e5d [core] add two new commands to output testbench parts 2023-11-02 16:06:48 -07:00
tangxifan 3d4f1505b6 [core] code format 2023-10-20 22:02:56 -07:00
tangxifan 66c3226fad [core] now follow module unique index when naming grouped configuration memories 2023-10-20 22:01:19 -07:00
tangxifan e4b204f2e4 [core] code format 2023-10-20 21:14:07 -07:00
tangxifan 76a4b8a82b [core] remove the prefix of grouped memory blocks 2023-10-20 21:13:37 -07:00
tangxifan 5bae2bf54d [core] code format 2023-10-19 23:05:49 -07:00
tangxifan 4b00651a46 [core] now name indexing is applied to netlist names 2023-10-19 23:03:48 -07:00
tangxifan 7ba6795fe2 [core] fixed a bug 2023-10-06 18:50:26 -07:00
tangxifan 83ef35b2da [core] fixed a bug 2023-10-06 18:47:20 -07:00
tangxifan 3440768840 [core] code format 2023-10-06 18:37:54 -07:00
tangxifan e102c9bddc [core] fixed a bug 2023-10-06 18:37:28 -07:00
tangxifan 93cbbf2045 [core] code format 2023-10-06 18:20:55 -07:00
tangxifan b07111497c [core] enable options in xml writers 2023-10-06 18:20:17 -07:00
tangxifan ae63c9d441 [core] code format 2023-10-06 17:28:25 -07:00
tangxifan 1e8bf1cece [core] deploy options 2023-10-06 17:28:02 -07:00
tangxifan f30663f708 [core] code format 2023-10-06 14:08:09 -07:00
tangxifan 108bbad8d4 [core] syntax 2023-10-06 14:07:44 -07:00
tangxifan 80856f1b70 [core] adding new options and rewrite options for bitfile writer 2023-10-06 13:54:29 -07:00
tangxifan a15db83267 [core] code format 2023-09-26 11:41:11 -07:00
tangxifan ea91182216 [core] check option conflicts 2023-09-26 11:40:42 -07:00
tangxifan c4bce834e4 [core] code format 2023-09-25 22:34:39 -07:00
tangxifan 5aa206e616 [core] fixed some bugs 2023-09-25 22:27:24 -07:00
tangxifan 1624dc9764 [core] code format 2023-09-25 21:13:50 -07:00
tangxifan 76f446caec [core] fixed a bug 2023-09-25 21:13:11 -07:00