Commit Graph

1721 Commits

Author SHA1 Message Date
tangxifan 523f9ac391 start implement openfpga shell and use vpr as a macro 2020-01-22 20:20:10 -07:00
tangxifan f6a36e8f76 Merge branch 'refactoring' into dev 2020-01-22 19:52:31 -07:00
tangxifan e983966a08 add macro function support to openfpga shell and update unit test 2020-01-22 19:30:36 -07:00
tangxifan 6309ef2db4 Merge branch 'refactoring' into dev 2020-01-22 17:21:21 -07:00
tangxifan 558f0bb1bd bug fixing in shell echo messages and add a test script 2020-01-22 17:11:24 -07:00
tangxifan 9b79bb2114 Merge branch 'refactoring' into dev 2020-01-22 16:52:23 -07:00
tangxifan bb8ef9614f change to namespace openfpga and bug fixed to avoid easy crash due to wrong options 2020-01-22 16:49:32 -07:00
tangxifan f8c5c1a117 update shell with new function binding strategy and new help desk print-out 2020-01-22 16:05:14 -07:00
tangxifan 7073e4d082 add shell unit test 2020-01-21 22:59:53 -07:00
tangxifan 4f26e2519f add shell interface and command execution 2020-01-21 20:46:24 -07:00
tangxifan 363ab382e5 add shell data structure 2020-01-21 17:24:49 -07:00
tangxifan b53897b838 add how-to-use for command data structure 2020-01-20 22:53:11 -07:00
tangxifan 7a5b36fe52 Add echo command and unit test for command parser 2020-01-20 20:31:16 -07:00
tangxifan 3ae80a192f add command echo functionality for mini shell 2020-01-20 19:42:43 -07:00
tangxifan acdb3818c2 start developing mini shell for open fpga 2020-01-20 18:14:24 -07:00
tangxifan 16752b7e39 update on sample arch 2020-01-20 12:42:08 -07:00
tangxifan 4c5917ac97 Merge branch 'refactoring' into dev 2020-01-19 15:01:09 -07:00
tangxifan 07994d424c add XML parser and writer for direct connection 2020-01-19 15:00:19 -07:00
tangxifan 10336cbe67 add XML parser and writer for routing circuit definition for OpenFPGA architecture 2020-01-19 14:44:27 -07:00
tangxifan ebe46d15a9 add XML parser, writer and linker for configuration protocol data structure 2020-01-18 21:19:20 -07:00
tangxifan 9693c3a12d add XML writer for simulation setting object 2020-01-18 16:41:42 -07:00
tangxifan bc3130d196 add XML parser for simulation setting 2020-01-18 15:40:20 -07:00
tangxifan 2a902c7e55 add mutators to simulation setting data structure 2020-01-18 14:07:37 -07:00
tangxifan 0de9908d52 add accessors to simulation setting data structure 2020-01-18 12:51:25 -07:00
tangxifan 7a46c85cb0 reorganize and clean-up sample architecture 2020-01-18 10:50:15 -07:00
tangxifan c9da3d5207 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-01-17 20:05:33 -07:00
tangxifan ab1b1b7e02 add XML writer for technology library 2020-01-17 20:02:56 -07:00
tangxifan df68dddb2a Merge branch 'refactoring' into dev 2020-01-17 19:03:57 -07:00
tangxifan 8f2936af54 finish XML parser for technology library 2020-01-17 17:43:55 -07:00
tangxifan e54760c677 add XML parsing for transistors and RRAM parameters in technology library 2020-01-17 17:32:42 -07:00
tangxifan d48a888804 add XML parsing for design parameters in technology library 2020-01-17 17:22:09 -07:00
tangxifan de0bcc96fb add missing file about XML parsers for technology library 2020-01-17 17:16:32 -07:00
tangxifan d58186507c add XML parsing for device model library settings 2020-01-17 17:15:58 -07:00
tangxifan 88a96673e3 rename some methods in technology library and start building associated XML parser 2020-01-17 16:44:57 -07:00
tangxifan 6a17abf257 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-01-17 15:36:22 -07:00
tangxifan b1501223cc bug fixed in SDC for CBs and SBs: remove useless module names 2020-01-17 15:33:50 -07:00
tangxifan 4bb0da5a69 bug fixing for direct connection when pin duplication is applied 2020-01-17 15:33:50 -07:00
tangxifan d4b5171fa2 add comments to technology library 2020-01-17 15:31:44 -07:00
Laboratory for Nano Integrated Systems (LNIS) c68f373917
Merge pull request #41 from LNIS-Projects/dev
bug fixed in SDC for CBs and SBs: remove useless module names
2020-01-17 15:29:00 -07:00
tangxifan 313922f03f add internal linker to technology library 2020-01-17 15:04:00 -07:00
tangxifan edaaa00c1d added mutators for technology library 2020-01-17 14:46:09 -07:00
tangxifan 6b703a4fc5 add accessors to technology library data structure 2020-01-17 13:34:32 -07:00
tangxifan 622ba9bb8c bug fixed in SDC for CBs and SBs: remove useless module names 2020-01-17 11:24:33 -07:00
tangxifan 771f2d9c37 developing data structure TechnologyLibrary to store technology-related information 2020-01-17 10:17:15 -07:00
tangxifan aa070b2a41 further clean-up sample arch.xml 2020-01-17 09:38:35 -07:00
tangxifan 910c69d7e5 clean up and reorganize XML about technology library 2020-01-17 09:24:58 -07:00
tangxifan 5c69f57559 sample_arch:move cmos/rram variation to technology library XML nodes 2020-01-16 20:58:45 -07:00
tangxifan 95edd3c091 clean up the sample arch 2020-01-16 20:52:47 -07:00
tangxifan a598929fe7 add circuit library checker in the test 2020-01-16 20:25:00 -07:00
tangxifan f7a7c56366 move OpenFPGAArch to openfpga namespace 2020-01-16 20:22:56 -07:00