tangxifan
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288294c23a
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add fast configuration test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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73d4c835b7
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add regression test case for memory bank
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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a1ec6833c2
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add memory bank example arch xml
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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e14c39e14c
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update Verilog full testbench generation to support memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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51e1559352
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add fabric bitstream support for memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0e16ee1030
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add configuration bus nets for memory bank decoders at top module
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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c00653961e
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minor format fix in documentation
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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ad7422359d
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deploy compact constant values in Verilog codes
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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0931eccbf6
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update documentation for the fast configuration options
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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fe2ba7d50a
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update documentation for standalone configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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c456ef4d00
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deploy the standalone preconfig testcase to CI
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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2def059b5b
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add standalone configuration protocol to pre config test cases
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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1fedd00912
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deploy the flatten configuration memory testcase to CI
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8ec8ac4118
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bug fixed in flatten memory organization. Passed verification
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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5f6a790eff
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add new test cases for the standalone memory configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8b5b221a21
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add new architecture for standalone memory organization
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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b9aac3cbdf
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updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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fbe05963e0
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add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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d2d443a988
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start developing memory bank and standalone configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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9a6a5e3310
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deploy fast configuration testcase to CI
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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9e176b8d38
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add fast configuration stats to log
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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a5138113e4
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add fast configuration testcase
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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22648cdb9c
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deploy the preconfig testbench cases to CI
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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05aa166a9e
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add preconfig testbench cases to regression tests for different configuration protocols
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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827e2e6713
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file moving in regression tests
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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de07712a3a
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update documentation about the frame-based configuration protocol
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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cdc2237008
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deploy frame-based configuration protocol to travis CI
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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b5e5182f52
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frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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583c15131b
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change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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31c9a011dd
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keep bug fixing for arch decoders
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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b8c449d520
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add comments for decoding functions to help debugging the frame-based decoders
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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bdc9efb38f
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bug fix in top-level testbench for frame-based decoders
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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986956e474
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bug fix for arch decoder Verilog codes. Now Modelsim compiles ok.
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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6a72c66eb8
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bug fixed for frame-based configuration memory in top-level full testbench
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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f5968fda52
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add configurable latch Verilog codes
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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8aa665b3b2
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bug fix in the Verilog codes for frame decoders
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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1e73fd6def
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create configuration frame example script
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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8298bbff78
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bug fixed in the fabric bitstream for frame-based configurable memories.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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bf9f62f0f7
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keep bug fixing for frame-based configuration protocol.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a0d3b4e95
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fix the broken CI/regression tests due to incorrect file path
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3fa3b17061
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start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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ece651ade2
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bug fixed in the configuration chian errrors
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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cff5b5cfc1
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break the configuration testbench. This commit is to spot which modification leads to the problem
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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85921dcc05
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add fabric bitstream builder for frame-based configuration protocol
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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8c14cced84
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start improve fabric bitstream database to support frame-based configuration protocol
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2020-06-11 19:31:09 -06:00 |