c96f899c53
[core] code format
2024-07-10 15:07:26 -07:00
a4538fb25b
[core] now supports to_pin in building clock network for internal driver
2024-07-10 15:01:18 -07:00
b2fc47a12a
[core] reworked i/o for clock network files
2024-07-10 14:34:54 -07:00
079e6f2fca
[core] add new syntax to support from_pin and to_pin for internal driver in clock network
2024-07-10 14:28:28 -07:00
0f78803759
[core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs
2024-07-09 20:47:15 -07:00
578d7c8ec0
[core] fixed a bug on region tap point identification
2024-07-01 20:58:41 -07:00
73b30841a7
[lib] typo
2024-07-01 20:56:27 -07:00
60e6e27e54
[core] fixed a bug on tap point identificatin
2024-07-01 20:45:55 -07:00
a85a6f1674
[core] code format
2024-07-01 17:57:10 -07:00
70428fd969
[lib] add sanity checks on global port name and clock network's global port name
2024-07-01 17:56:29 -07:00
df23daf026
[lib] sanity check on global port name and from pin name of tap points
2024-07-01 17:37:16 -07:00
7c487eadc9
[core] now clock network keep port info in a native data structure
2024-07-01 16:58:23 -07:00
3afb92d6a5
[core] code format
2024-06-30 22:48:15 -07:00
1fd974d544
[core] fixed a bug where clock network size cannot impact global port on top module
2024-06-29 17:35:47 -07:00
34fb003911
[core] replace width syntax with global port name
2024-06-29 10:46:00 -07:00
5cfd23747b
[core] code format
2024-06-28 13:47:03 -07:00
4185235a69
[core] now clock routing is based on tree expansion. Unused part can be disconnected
2024-06-27 15:02:20 -07:00
cab649893b
[core] update clock architecture
2024-06-26 18:06:39 -07:00
59be95b227
[core] code format
2024-06-26 17:58:26 -07:00
3efa97b84e
[core] support coordinate on clock taps
2024-06-26 17:40:11 -07:00
3b25e42720
[lib] syntax
2024-06-26 15:51:00 -07:00
381a8cb535
[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
2024-06-26 15:41:56 -07:00
4640e74e7e
[core] code format
2024-06-25 12:25:16 -07:00
66af73e91e
[lib] now accept reset and set in programmable clock network
2024-06-25 12:24:46 -07:00
7bcbd8a88b
[core] code format
2024-06-25 11:44:50 -07:00
3b2c13402a
[core] syntax
2024-06-25 11:44:25 -07:00
31d4b4c402
[core] now support add internal drivers to clock tree
2024-06-25 11:27:22 -07:00
272d78eb43
[test] add a new unit test
2024-06-24 19:13:36 -07:00
22bee35fd1
[lib] mem allocate
2024-06-24 18:47:56 -07:00
36ef555dda
[lib] add example arch for clock arch with internal drivers
2024-06-24 18:33:47 -07:00
2eda2825b7
[lib] syntax
2024-06-24 18:28:42 -07:00
0c442f6238
[lib] add syntax to support internal drivers in clock network parsers
2024-06-24 17:54:58 -07:00
2193f108ee
[core] add debugging messages
2024-06-21 18:42:35 -07:00
ecd31955b1
[core] code format
2024-06-21 17:11:32 -07:00
3ddaefc2a2
[lib] syntax
2024-06-21 17:02:37 -07:00
1ab75cf76c
[lib] now link clock arch supports tap and driver default switches
2024-06-21 16:52:22 -07:00
9ccd14bf4d
[lib] now default switch of clk ntwk is split to default_tap_switch and default_driver_switch
2024-06-21 16:45:05 -07:00
ca6e2f9831
[core] code format
2024-05-20 13:41:35 -07:00
b15e169490
[core] fixed a bug where wire model is expected on direct connections
2024-05-20 12:45:49 -07:00
9d87e99539
[lib] typo on keywords in XML parser
2024-05-20 11:15:43 -07:00
926b9e9739
[core] code format
2024-05-18 12:33:19 -07:00
3b93bea3d1
[core] syntax
2024-05-18 12:29:38 -07:00
be1d7517c9
[doc] rework out-of-date syntax
2024-05-17 19:25:35 -07:00
0d8c21ca84
[core] add new type 'part_of_cb' for tile direct connections
2024-05-17 18:59:53 -07:00
36d37289fe
[lib] add missing header required by clang-11+
2024-05-05 21:21:36 -07:00
03bea1c566
[lib] code format
2024-05-05 18:47:37 -07:00
df3b4357fc
[lib] add header to pass Gcc-12
2024-05-05 18:24:44 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
39a012b939
Support checking illegal pin constraint (use loc as key and update message format)
2024-03-04 12:41:19 +08:00
tangxifan
chungshien
Victor