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2065 Commits

Author SHA1 Message Date
tangxifan 23aef96d3a add behavioral verilog test case to Travis CI 2020-04-12 19:55:47 -06:00
tangxifan 11e9014542 add notes about debugging the aib FPGA 2020-04-12 19:07:53 -06:00
tangxifan a614e5aad9 add long adder chain to Travis CI 2020-04-12 15:43:19 -06:00
tangxifan f71a85a1d4 add test cases on different routing multiplexer circuit designs to Travis CI 2020-04-12 15:39:45 -06:00
tangxifan 214d98fbcd add register chain and scan chain to Travis CI 2020-04-12 15:28:22 -06:00
tangxifan 148cc74d6a add io test cases to Travis CI 2020-04-12 15:01:47 -06:00
tangxifan da5af8f0e0 try to add aib test case. bug found 2020-04-12 14:54:45 -06:00
tangxifan 28cb412359 add test case of wide BRAM 16k to Travis CI 2020-04-12 14:37:08 -06:00
tangxifan 5d665aa04b reshape bram test case 2020-04-12 14:32:09 -06:00
tangxifan 600a48edc7 add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
tangxifan 2444752de8 add untileable test case to Travis CI 2020-04-12 14:08:24 -06:00
tangxifan cc7adae91e deploy openfpga shell in Travis CI 2020-04-12 12:57:13 -06:00
tangxifan d806ad3148 add testcases using openfpga_shell in openfpga_flow 2020-04-12 12:54:21 -06:00
tangxifan 68fd296e14 add more test vpr architecture to regression tests 2020-04-12 12:49:16 -06:00
ganeshgore 80bdb41df6 Updated task file to run formal verification 2020-04-11 18:30:21 -06:00
ganeshgore e6de0cdce0 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-04-11 18:05:31 -06:00
tangxifan 49ddbf98c3 add more testing architecture to openfpga_flow 2020-04-11 18:01:09 -06:00
tangxifan 130b78ca74 update arch in openfpga_flow 2020-04-11 18:00:37 -06:00
tangxifan c67a480d6f Merge branch 'ganesh_dev' into dev 2020-04-11 16:48:56 -06:00
ganeshgore f6b3c5854a Bugfix : 
+ OpenFPGA template variables update
+ Default path for the verilog netlist
 2020-04-11 16:45:22 -06:00
Xifan Tang b4542ea34b minor fix on doc about the global and general purpose port 2020-04-09 17:10:04 -06:00
tangxifan 6db4a1290d
Merge pull request #51 from LNIS-Projects/ganesh_dev 
Ganesh dev
 2020-04-08 21:59:28 -06:00
ganeshgore 8ea272dc2c Patched the OpenFPGA shell execution bug 2020-04-08 21:28:14 -06:00
ganeshgore 8267d78b01 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-04-08 18:40:39 -06:00
Xifan Tang d99776b260 update documentation on the global I/O ports 2020-04-08 18:18:53 -06:00
tangxifan e6c896d583 now inout must be global port and I/O port so that it will appear in the top-level module 2020-04-08 16:54:08 -06:00
tangxifan b9dab2baaf add exit codes to command execution in shell context 2020-04-08 16:18:05 -06:00
Xifan Tang b9ade3fcb6 documentation update to introduce new features in script mode of OpenFPGA shell 2020-04-08 14:13:28 -06:00
tangxifan caef468c95 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-04-08 12:56:06 -06:00
tangxifan 1fb37f4c71 improve directory creator to support same functionality as 'mkdir -p' 2020-04-08 12:55:09 -06:00
ganeshgore 583a4d8767 Fixed bug in openfpga_flow script 2020-04-08 12:04:08 -06:00
ganeshgore 75edf5912f Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-04-08 11:39:25 -06:00
tangxifan f9e055c551 Merge branch 'ganesh_dev' into dev 2020-04-08 10:56:16 -06:00
tangxifan e31dc1f2f2 openfpga shell now support continued line charactor '\' 2020-04-07 21:27:51 -06:00
tangxifan 33315f0521 now openfpga shell allow empty space at beginning and end of each line in script mode 2020-04-07 20:46:45 -06:00
tangxifan 0b1c8ac139 bug fixed in identifying the physical interconnect for pb_graph nodes 2020-04-07 19:46:42 -06:00
tangxifan 62276f9e28 minor code format 2020-04-07 18:43:11 -06:00
tangxifan dd4f83a374 bug fixing to constant string to display interconnect names 2020-04-07 18:28:19 -06:00
tangxifan ff7ea99381 bug fixed in register scan-chain architecture 2020-04-07 17:06:16 -06:00
tangxifan 2342d7cdc6 minor tweak on the scan-chain support in VPR8 as well as architecture file 
Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
 2020-04-07 17:03:44 -06:00
tangxifan 50bb04d496 add scan-chain test case. Debugging on the way 2020-04-07 16:50:41 -06:00
tangxifan cbcd1d20d4 fixed memory leakage in pb_pin fixup 2020-04-07 16:24:04 -06:00
tangxifan 5a04da2082 fix memory leakage in openfpga title 2020-04-07 16:14:41 -06:00
tangxifan 6daee8c2c8 bug fixed in the example architecture 2020-04-07 16:03:34 -06:00
tangxifan 628ea3b654 improve adder chain arch XML to support sequential output for sumout 2020-04-07 15:39:37 -06:00
tangxifan 26d1261c1f add test cases using shift registers 2020-04-07 15:09:10 -06:00
Xifan Tang 307ef58c45 update README to remove dead links 2020-04-07 12:30:23 -06:00
Xifan Tang 55e68896d6 doc update for the support on std cell MUX2 and examples 2020-04-07 12:01:13 -06:00
tangxifan e61e7167b3 update circuit model names in the example tree-like MUX architecture 2020-04-07 11:27:16 -06:00
tangxifan 0eeb8e5317 clean up example architecture XML by removing redundant syntax 2020-04-07 11:24:42 -06:00