tangxifan
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29da368742
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[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
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2020-10-30 10:46:47 -06:00 |
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tangxifan
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b701bd2640
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[Arch] Add multi-region architecture example for frame-based protocol
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2020-10-30 10:45:14 -06:00 |
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tangxifan
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1d930d1b5d
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[Architecture] Add missing arch files and bug fix
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2020-10-29 18:08:26 -06:00 |
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tangxifan
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153b265a6d
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[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
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2020-10-29 16:32:05 -06:00 |
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tangxifan
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7534474423
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[Arch] Add architecture for multiple-region memory banks
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2020-10-29 13:54:51 -06:00 |
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tangxifan
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c5bcd93408
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[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
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2020-10-13 11:57:21 -06:00 |
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tangxifan
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99b1e68d92
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[Architecture] Add architecture using GND as constant inputs for multiplexers
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2020-10-13 11:39:27 -06:00 |
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tangxifan
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d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
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d5c7411399
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[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
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2020-09-29 13:50:31 -06:00 |
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tangxifan
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23449dc5c3
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[Architecture] Add multiple region configuration chain architecture
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2020-09-29 13:46:40 -06:00 |
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tangxifan
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dcbd6a0614
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[Architecture] Add lib name to TGATE to test compatibility
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2020-09-25 21:08:12 -06:00 |
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tangxifan
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019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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tangxifan
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00bf775971
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[Architecture] Bug fix for adder renaming
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2020-09-24 20:54:18 -06:00 |
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tangxifan
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0a53a719bd
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[Architecture] Bug fix due to adder renaming
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2020-09-24 20:42:24 -06:00 |
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tangxifan
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bd0f0144a0
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[Architecture] Rename AIB architecture for the new cell naming
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2020-09-24 20:14:16 -06:00 |
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tangxifan
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4ada793c84
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[Architecture] Adapt openfpga architecture to follow the renamed adder cell
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2020-09-24 20:09:29 -06:00 |
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tangxifan
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4a0a448171
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[Architecture] Rename openfpga architecture for the I/O cell
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2020-09-24 19:56:01 -06:00 |
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tangxifan
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eb5fd1f44e
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[Architecture] Bug fix for architectures using scan-chain DFF cell
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2020-09-24 18:37:25 -06:00 |
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tangxifan
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60a14ccbd2
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[Architecture] Bug fix in architectures that use BRAM
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2020-09-24 18:20:55 -06:00 |
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tangxifan
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d51efd397f
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[Architecture] Bug fix for architectures using DFF cells
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2020-09-24 18:02:42 -06:00 |
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tangxifan
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3ade6d6ff5
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[Architecture] Bug fix for dff that are used in data path
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2020-09-24 17:53:30 -06:00 |
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tangxifan
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3e7c88eac8
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[Architecture] Bug fix in Verilog netlist for scan-chain DFF
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2020-09-24 17:41:03 -06:00 |
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tangxifan
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7494556316
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[Architecture] Bug fix for scan-chain FF cell
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2020-09-24 17:38:16 -06:00 |
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tangxifan
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49d6863641
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[Architecture] Bug fix for scan-chain FF cell renaming
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2020-09-24 17:33:14 -06:00 |
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tangxifan
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0a5369f919
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[Architecture] Adapt all the architecture files to use standard DFF cell
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2020-09-24 17:26:48 -06:00 |
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tangxifan
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fc154b8560
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[Architecture] Bug fix due to switching CCFF cell
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2020-09-24 16:45:56 -06:00 |
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tangxifan
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79875d5a91
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[Architecture] Bug fix in the configuration chain arch using both reset and set
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2020-09-24 15:27:26 -06:00 |
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tangxifan
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9cb67e6097
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[Architecture] Now all the configuration chain architecture use the DFFR cell by default
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2020-09-24 15:19:37 -06:00 |
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tangxifan
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178afb3c7f
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[Architecture] Add configuration chain architectures using different DFF cells
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2020-09-24 14:23:27 -06:00 |
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tangxifan
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98d88dc686
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[Architecture] Bug fix for vanilla memory organization
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2020-09-24 14:13:48 -06:00 |
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tangxifan
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539bb617f9
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[Architecture] Add reset test case for frame based configuration
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2020-09-24 12:17:18 -06:00 |
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tangxifan
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2add0406a7
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[Architecture] Update architecture files for new latch naming
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2020-09-24 12:14:03 -06:00 |
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tangxifan
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83971bba41
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[Architecture] Update cell ports for native SRAM cell
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2020-09-24 10:31:31 -06:00 |
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tangxifan
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56c9aab190
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[Architecture] Add architecture to use different SRAM cells for memory bank
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2020-09-24 10:15:08 -06:00 |
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tangxifan
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10b6e1dc0d
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[Architecture] bug fix for active-low
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2020-09-23 23:06:46 -06:00 |
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tangxifan
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5d60b4ef8c
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[Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set
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2020-09-23 23:02:49 -06:00 |
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tangxifan
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8e780635df
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[Regression Test] Rename test case in CI
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2020-09-23 22:59:46 -06:00 |
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tangxifan
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c7fc0178b0
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[Architecture] Rename to be consist with other architectures
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2020-09-23 22:57:06 -06:00 |
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tangxifan
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707300a6e4
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[Architecture] Bug fix for using both reset and set architecture
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2020-09-23 22:07:40 -06:00 |
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tangxifan
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77a1f99564
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[Architecture] Bug fix for architecture using set only
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2020-09-23 22:04:24 -06:00 |
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tangxifan
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9331ef941d
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[Architecture] Add architecture that use both set and reset signals
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2020-09-23 21:46:04 -06:00 |
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tangxifan
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7591060fbd
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[Architecture] Add configurable latch Verilog designs and assoicated architectures
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2020-09-23 21:45:06 -06:00 |
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tangxifan
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8fa4fa1125
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[Architecture] Add openfpga architecture using set signals for configurable latch
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2020-09-23 21:39:31 -06:00 |
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tangxifan
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2869eae8a9
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[Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol
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2020-09-23 20:43:15 -06:00 |
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tangxifan
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fc60b18191
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[Architecture] Now a regular flip-flop can be used in frame-based configuration
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2020-09-23 20:41:49 -06:00 |
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tangxifan
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8e4e66038a
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[Architecture] Bug fix for standalone memory
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2020-09-23 19:32:48 -06:00 |
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tangxifan
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1864b080a2
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[Architecture] Bug fix in configurable latch Verilog HDL
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2020-09-23 18:28:45 -06:00 |
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tangxifan
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ebb866d04a
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[Architecture] Patch frame based using ccff
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2020-09-23 18:04:14 -06:00 |
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tangxifan
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906191e931
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[Architecture] Use strict latch Verilog HDL in frame-based procotol
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2020-09-23 17:58:13 -06:00 |
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tangxifan
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1a2c66f07d
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[Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell
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2020-09-23 17:34:49 -06:00 |