Commit Graph

450 Commits

Author SHA1 Message Date
tangxifan d0fe8d96fa [Test] Update template scripts and assoicated test cases by offering more options 2022-02-14 16:03:48 -08:00
tangxifan 70363effa4 [Test] Add a new test to validate 8-bit counters using full testbenches 2022-02-14 15:57:55 -08:00
tangxifan 7ef808cbe4 [Test] Update pin constraints for different counter benchmarks 2022-02-14 15:28:03 -08:00
tangxifan 570c1b10dc [Test] Add dedicated pin constraints for counter designs 2022-02-14 13:54:48 -08:00
tangxifan 85011824e2 [Test] Enable Verilog-to-Verification flow for counter8 benchmarks 2022-02-14 13:15:55 -08:00
tangxifan 6630c17c23 [Test] Use preconfigured testbench template to run counter8 tests 2022-02-14 13:07:31 -08:00
tangxifan da3f9ccb80 [Test] Truncating counter designs in each task 2022-02-14 12:22:19 -08:00
tangxifan 0268814fc6 [Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests 2022-02-14 12:20:56 -08:00
tangxifan 532af96243 [Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench 2022-02-01 13:44:47 -08:00
tangxifan da8fc0f5d4 [Test] Add a new test case to validate ``--use_relative_path`` 2022-01-31 13:02:19 -08:00
tangxifan f8ef3df560 [Test] Now use 4x4 fabric in testing write_rr_gsb commands 2022-01-26 11:41:48 -08:00
tangxifan 3b7588cd48 [Test] Rename test case to be consistent with the name of options 2022-01-26 11:25:54 -08:00
tangxifan 6b26ed0819 [Test] Add test cases on writing gsb files 2022-01-26 11:22:39 -08:00
tangxifan 23795d6474 [Test] Update golden netlists 2022-01-25 20:37:08 -08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan fedb1bd2e3 [Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp 2022-01-25 16:41:36 -08:00
tangxifan 6e778a74ee [Test] Add golden reference for files outputted without time stamp 2022-01-25 16:24:25 -08:00
tangxifan 2bee59c6ca [Test] Add the testcase to validate ``--no_time_stamp`` 2022-01-25 16:21:15 -08:00
tangxifan dd803dd1de [Test] Remove unused tests 2022-01-25 16:16:58 -08:00
Aram Kostanyan 758453f725 Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections. 2022-01-21 02:21:00 +05:00
Aram Kostanyan 397f2e71f1 Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task. 2022-01-19 20:43:26 +05:00
Aram Kostanyan bd158311c5 Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark. 2022-01-18 14:07:41 +05:00
Aram Kostanyan 588ee14920 Merge branch 'master' into issue-483 2022-01-18 13:38:12 +05:00
Aram Kostanyan 6a4cc340a3 Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly. 2022-01-17 13:21:29 +05:00
Awais Abbas 598c5e6b75 Test case for yosys-only flow added 2022-01-14 15:37:47 +05:00
tangxifan 824a03bdca [Flow] Patch new test case 2022-01-02 20:20:36 -08:00
tangxifan 55da99f4ca [Flow] Add a new test case to validate DSP with registers 2022-01-02 20:08:23 -08:00
nadeemyaseen-rs 06fb4b0ece Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-25 00:00:22 +05:00
coolbreeze413 31379062e3 remove minor comments 2021-11-18 18:40:15 +05:30
nadeemyaseen-rs 1ea56b2d18 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-11-18 00:00:55 +05:00
coolbreeze413 91094305bd enable all tests except 15 and 19 2021-11-17 20:56:12 +05:30
coolbreeze413 840fa399c6 enable single counter test (fails, needs debug) 2021-11-09 21:36:33 +05:30
Aram Kostanyan b332a5a1b4 Added 'basic_tests/verific_test' test-case. 2021-11-01 18:20:57 +05:00
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 7f999d03c6 [Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade 2021-10-30 18:05:39 -07:00
tangxifan 370e3fef83 [Test] Now use pre-configured testbench when verifying signal gen microbenchmarks 2021-10-30 18:03:59 -07:00
tangxifan c8e9dfbeda [Test] bug fix 2021-10-30 16:50:57 -07:00
tangxifan a4cfc84930 [Test] Bug fix 2021-10-30 16:00:47 -07:00
tangxifan 335347a74f [Test] Bug fix 2021-10-30 15:48:25 -07:00
tangxifan be47e78289 [Arch] Change arch for Sapone test 2021-10-30 15:23:19 -07:00
tangxifan ad5cce0ae8 [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals 2021-10-30 15:11:07 -07:00
tangxifan 40d11a45d9 [Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade 2021-10-30 14:49:56 -07:00
tangxifan 16de60e943 [Test] Turn off ACE2 run in bitstream generation only flows 2021-10-30 12:31:14 -07:00
tangxifan b2c4e3314e [Test] Bug fix in test cases 2021-10-11 10:28:09 -07:00
tangxifan 8566e2a0cd [Test] Renaming test case to follow naming convention as other fabric key test cases 2021-10-11 09:56:23 -07:00
tangxifan b8b02d37d5 [Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file 2021-10-11 09:53:23 -07:00
tangxifan 6122863548 [Test] Add a test case to validate the multi-shift-register-chain QL memory bank 2021-10-09 20:44:28 -07:00
tangxifan a1eaacf5a8 [Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency 2021-10-06 12:12:15 -07:00
tangxifan b98a8ec718 [Test] Added the dedicated test case for fixed shift register clock frequency 2021-10-06 12:09:26 -07:00
tangxifan 189ade6c1e [Test] Bug fix 2021-10-05 19:17:34 -07:00