Commit Graph

68 Commits

Author SHA1 Message Date
tangxifan 1e183e7885 refactored shared config bits calculation 2019-10-06 16:57:53 -06:00
tangxifan 433fc73460 refactored local encoder support for Verilog MUX generation 2019-09-27 23:10:43 -06:00
tangxifan 167778cf57 refactoring MUX Verilog instanciation in Switch block 2019-09-27 16:05:47 -06:00
tangxifan ead014e7d8 refactoring the configuration bus Verilog generation for MUXes 2019-09-27 11:47:34 -06:00
tangxifan 091bbd4d9c start refactoring the num_config_bits for circuit model 2019-09-26 22:53:07 -06:00
tangxifan f0589cc2cf refactoring mux Verilog generation for switch blocks 2019-09-26 20:59:19 -06:00
tangxifan e0b253d30a minor fix for non-LUT intermedate buffer case 2019-09-18 15:15:03 -06:00
tangxifan 62853c092f refactoring local encoders. Ready to plug in 2019-09-10 15:16:29 -06:00
tangxifan 59edd49862 refactored CMOS MUX buffering 2019-09-06 16:39:34 -06:00
tangxifan bc9d95408e bug fixed and refactored intermediate buffer addition 2019-09-05 16:09:28 -06:00
tangxifan e623c19055 implementing mux Verilog generation. Bugs detected, fixing ongoing 2019-09-04 23:54:53 -06:00
tangxifan fde9c8b4ec add frac_lut outputs to mux_graph generation 2019-09-03 23:19:24 -06:00
tangxifan b6bb433edc bug fixing for datapath mux size in Verilog generation 2019-09-03 18:09:21 -06:00
tangxifan ab6f1a5461 add mux output ids for mux_graph 2019-08-26 21:21:50 -06:00
tangxifan c43fabb43c developed verilog instance writer. refactoring on mux ongoing 2019-08-25 10:31:45 -06:00
tangxifan fe7dfd59c3 Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-08-24 23:54:37 -06:00
tangxifan 63f40f48fa develop and plug mux_lib_builder, refactoring the mux submodule generation 2019-08-24 19:23:33 -06:00
tangxifan 5e156dc725 minor fix for OSX and update travis using ccache to speed up compilation 2019-08-21 15:25:36 -06:00
tangxifan 29104b6fa5 rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
tangxifan a7ac1e4980 remame methods in circuit_library 2019-08-20 15:24:53 -06:00
tangxifan 69039aa742 developed subgraph extraction and start refactoring mux generation 2019-08-20 15:24:53 -06:00
tangxifan bee070d7cc start plug in MUX library 2019-08-20 15:24:53 -06:00
tangxifan 893683fa95 start developing mux library 2019-08-20 15:24:53 -06:00
tangxifan 153d506abb add graph-based mux decoding function 2019-08-20 15:24:52 -06:00
tangxifan dcca9f4f0f finish mux graph builders 2019-08-20 15:24:52 -06:00
tangxifan 638969c3c9 adding mux graph data structures 2019-08-20 15:24:52 -06:00
tangxifan 0b8473e960 start developing graphs for muxes, with aims to simplify netlist and bitstream generation 2019-08-20 15:24:52 -06:00
tangxifan 4cffd8ac2d keep route file updated with tileable rr_graph 2019-08-13 15:37:42 -06:00
tangxifan cffdebd912 bug fixed for the tileable RR graph generator for heterogeneous blocks 2019-07-11 21:02:09 -06:00
tangxifan 65f696c1d7 fix critical bugs in rectangle floorplan 2019-07-09 17:41:20 -06:00
tangxifan 76fefdb876 bug fixing in Fc_in and be serious in the performance of rr_graph 2019-07-05 16:23:15 -06:00
tangxifan c62762ce59 bug fixing in assign ipins to tracks using Fc_in 2019-07-05 13:42:22 -06:00
tangxifan 64d8e9663a minor fix to satisfy Fc_in and Fc_out 2019-07-05 13:13:35 -06:00
tangxifan 3077efa74f add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tangxifan 1a1da30ae9 fixed a critical bug in using tileable route chan W 2019-07-03 16:46:43 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tangxifan 4392c6bc3a bug fixing in fpga_flow scripts and add more print-out message for VPR 2019-07-02 15:34:59 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 15c536e9b4 minor fixing in printing the rr_node stats 2019-06-27 16:34:21 -06:00
tangxifan 42f85004b6 fix bugs in finding the ending SB of a rr_node 2019-06-26 14:13:41 -06:00
tangxifan 3c0ef2067d fixed critical bugs in pass_tracks identification and update regression test for tileable arch 2019-06-25 21:59:38 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
tangxifan 785b560bd5 sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now 2019-06-24 22:46:56 -06:00
tangxifan fd301eeb66 many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
tangxifan 0d62661c71 bug fixing and spot critical bugs in directlist parser 2019-06-23 20:52:38 -06:00
tangxifan cdd4af9c58 vpr likes the tileable rr_graph while fpga_x2p does not 2019-06-23 18:11:13 -06:00
tangxifan 59df305668 bug fixing and reorganize rr_graph builder source files 2019-06-23 16:40:13 -06:00
tangxifan 2837f44df2 bug fixing for tileable rr_graph generator. 2019-06-22 20:41:06 -06:00
tangxifan 7c38b32eb1 keep bug fixing for tileable rr_graph generator 2019-06-21 22:51:11 -06:00