tangxifan
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7206cafc0e
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[Tool] Minor bug fix
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2020-12-04 17:18:02 -07:00 |
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tangxifan
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1c3f625e41
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[Arch] Force empty tiles at corners for tileable I/O arch example
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2020-12-04 17:11:06 -07:00 |
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tangxifan
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29fd13a42a
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[Tool] Relax restrictions on I/O location in tileable rr_graph builder
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2020-12-04 17:07:01 -07:00 |
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tangxifan
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0cb8457e21
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[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
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tangxifan
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186eb0f0a4
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[Arch] Add tileable I/O architecture example
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2020-12-04 15:59:39 -07:00 |
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tangxifan
|
406edeec89
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[Doc] Typo fix
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2020-12-04 15:07:02 -07:00 |
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tangxifan
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4fe190fa7e
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
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tangxifan
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4aa6264b1c
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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tangxifan
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b661c39b04
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[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
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2020-12-02 19:36:36 -07:00 |
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tangxifan
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412fb5bb31
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[Arch] Bug fix due to valid default value parser
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2020-12-02 17:51:50 -07:00 |
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tangxifan
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8350b0f911
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[Doc] Update documentation about default value definition in tile annotation
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2020-12-02 17:08:34 -07:00 |
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tangxifan
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d195b9e32c
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[Tool] Bug fix in XML syntax to define default values for a global tile port
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2020-12-02 17:03:48 -07:00 |
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tangxifan
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290ff028cd
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[Test] Add global_tile_reset test case to CI
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2020-11-30 18:12:47 -07:00 |
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tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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c7604ab94f
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[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
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2020-11-30 18:02:00 -07:00 |
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tangxifan
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ff53d2c375
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[HDL] Add new Scan-chain DFF cell
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2020-11-30 17:54:10 -07:00 |
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tangxifan
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ad703ad85b
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[HDL] Add new gpio cell with protection circuitry
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2020-11-30 17:52:39 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
|
7a0a3398d4
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[Arch] Add new architecture to test global reset ports defined thru tile ports
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2020-11-30 17:43:41 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
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tangxifan
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fc79e83e44
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[Doc] Update README with latest Github Action badge
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2020-11-30 11:57:08 -07:00 |
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tangxifan
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cc0114459a
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[Doc] Enrich examples for LUT circuit models
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2020-11-26 13:03:12 -07:00 |
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tangxifan
|
62e804215b
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[Doc] Add svg figures for LUT examples
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2020-11-26 12:35:39 -07:00 |
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tangxifan
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dc5e2c99af
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[Test] Add native fracturable LUT4 test to CI
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2020-11-25 23:02:18 -07:00 |
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tangxifan
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3a708cff21
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[Tool] Bug fix to enable nature fracturable LUT design
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2020-11-25 23:01:18 -07:00 |
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tangxifan
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a60bd4d14a
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[Arch] Bug fix in nature fracturable architecture
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2020-11-25 22:48:26 -07:00 |
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tangxifan
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b8559249dc
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[Test] Bug fix in task configuration file
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2020-11-25 22:23:27 -07:00 |
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tangxifan
|
26e4db56ad
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[Test] Add new test case for the native fracturable LUT4
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2020-11-25 22:21:23 -07:00 |
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tangxifan
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17070c6405
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[Doc] Update README in openfpga arch directory for native fracturable LUT design
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2020-11-25 22:19:20 -07:00 |
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tangxifan
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f6a667de58
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[Arch] Add openfpga architecture using native fracturable LUT
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2020-11-25 22:18:03 -07:00 |
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tangxifan
|
eda671592e
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[Doc] Update README about new keyword about fracturable LUT
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2020-11-25 22:12:56 -07:00 |
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tangxifan
|
0f841aa6d1
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[Arch] Add an example architecture using native fracturable LUT
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2020-11-25 22:11:14 -07:00 |
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tangxifan
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d2954f025f
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Merge branch 'master' into dev
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2020-11-24 20:08:44 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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e87f29784d
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Merge pull request #133 from LNIS-Projects/github-actions-test
Use GitHub Actions as CI
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2020-11-24 20:06:48 -07:00 |
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tangxifan
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96a99fcb6b
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[Test] Change to short build name and see if ccache is working or not
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2020-11-24 18:58:06 -07:00 |
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tangxifan
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df98c83d33
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[Test] Keep trying the paths for ccache
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2020-11-24 18:10:52 -07:00 |
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tangxifan
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91709abe80
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[Test] Try to get the correct path to github workspace
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2020-11-24 18:00:59 -07:00 |
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tangxifan
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9f956502b7
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[Test] keep fixing the path to ccache file
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2020-11-24 17:56:08 -07:00 |
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tangxifan
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6b757e2dca
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[Test] Bug fix in ccache path
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2020-11-24 17:50:22 -07:00 |
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tangxifan
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0af1c0468e
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[Test] Spot cache file and try to use it
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2020-11-24 17:41:27 -07:00 |
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tangxifan
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df317271fd
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[Test] Try to check if .ccache is in the build directory
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2020-11-24 16:54:55 -07:00 |
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tangxifan
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c7d288c043
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[Test] Try to new cache action version to see if problem is solved
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2020-11-24 16:50:29 -07:00 |
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tangxifan
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cba07b6020
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[Test] Now travis and github actions share the common regression test scripts
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2020-11-24 15:58:09 -07:00 |
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tangxifan
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ab3c41715e
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[Doc] Update badges for the github actions
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2020-11-24 15:44:16 -07:00 |
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tangxifan
|
ca593f23fc
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[Test] Merge reg test to build tests on Github Actions
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2020-11-24 15:32:45 -07:00 |
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tangxifan
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27e68f1ea2
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[Test] Add check ccache size
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2020-11-24 15:20:38 -07:00 |
|
tangxifan
|
955e49dca1
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[Test] bug fix for ccache and enhance printing messages
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2020-11-24 15:10:33 -07:00 |
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tangxifan
|
54db85c2f6
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[Test] Correct the path to test scripts
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2020-11-24 14:27:40 -07:00 |
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tangxifan
|
8bbbec37a3
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[Doc] Add badges for Github Actions to frontpage README
|
2020-11-24 13:56:01 -07:00 |
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tangxifan
|
03f18b776c
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[Test] typo fix
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2020-11-24 13:44:14 -07:00 |