tangxifan
|
3fb891094b
|
[doc] add new syntax
|
2024-06-27 11:02:37 -07:00 |
|
tangxifan
|
6fceb81110
|
[core] code format
|
2024-06-27 10:19:40 -07:00 |
|
tangxifan
|
64a7a4ce26
|
[core] syntax
|
2024-06-27 10:19:14 -07:00 |
|
tangxifan
|
9ce552495a
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[core] now internal drivers can be routed in dedicated clock network
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2024-06-27 10:17:08 -07:00 |
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tangxifan
|
53c155c02b
|
Merge pull request #1731 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2024-06-27 09:52:57 -07:00 |
github-actions[bot]
|
1f4fda25eb
|
Updated Patch Count
|
2024-06-27 16:44:38 +00:00 |
|
tangxifan
|
39e0c1b635
|
Merge pull request #1730 from lnis-uofu/dependabot/submodules/yosys-07daf61
Bump yosys from `1288166` to `07daf61`
|
2024-06-27 09:44:16 -07:00 |
dependabot[bot]
|
ec85bfc704
|
Bump yosys from `1288166` to `07daf61`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `1288166` to `07daf61`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](1288166f7a...07daf61ae6)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-27 06:41:45 +00:00 |
|
tangxifan
|
ac1ad52795
|
[core] code format
|
2024-06-26 22:47:29 -07:00 |
|
tangxifan
|
5d0b0b9a8c
|
[core] now global nets mapping are applied to clock routing
|
2024-06-26 22:46:12 -07:00 |
|
tangxifan
|
d5d9531eec
|
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
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2024-06-26 21:52:45 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
59be95b227
|
[core] code format
|
2024-06-26 17:58:26 -07:00 |
|
tangxifan
|
59404e5487
|
[core] add verbose output
|
2024-06-26 17:55:23 -07:00 |
|
tangxifan
|
576a861b8d
|
[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
|
2024-06-26 17:54:31 -07:00 |
|
tangxifan
|
3efa97b84e
|
[core] support coordinate on clock taps
|
2024-06-26 17:40:11 -07:00 |
|
tangxifan
|
3b25e42720
|
[lib] syntax
|
2024-06-26 15:51:00 -07:00 |
|
tangxifan
|
381a8cb535
|
[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
|
2024-06-26 15:41:56 -07:00 |
|
tangxifan
|
bd05bc4c24
|
Merge pull request #1729 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-25 20:16:17 -07:00 |
|
github-actions[bot]
|
3ebaaa700e
|
Updated Patch Count
|
2024-06-26 01:31:49 +00:00 |
|
tangxifan
|
52e2fed5f4
|
Merge pull request #1726 from lnis-uofu/xt_ci
Use a new version of cancel-previous-flow due to node16 deprecation
|
2024-06-25 18:31:31 -07:00 |
|
tangxifan
|
c07e35136b
|
[ci] now use download-artifact v4
|
2024-06-25 16:46:33 -07:00 |
|
tangxifan
|
ec1ad94d4a
|
[doc] add syntax about internal drivers
|
2024-06-25 13:06:47 -07:00 |
|
tangxifan
|
c99178f350
|
[test] fixed a bug on pin locations
|
2024-06-25 12:34:52 -07:00 |
|
tangxifan
|
4640e74e7e
|
[core] code format
|
2024-06-25 12:25:16 -07:00 |
|
tangxifan
|
66af73e91e
|
[lib] now accept reset and set in programmable clock network
|
2024-06-25 12:24:46 -07:00 |
|
tangxifan
|
fbece49047
|
[core] fixed a bug where unexpected OPINs are added as internal drivers
|
2024-06-25 12:07:19 -07:00 |
|
tangxifan
|
2cbb04b90d
|
[test] add a new testcase to validate programmable clock network with internal drivers
|
2024-06-25 11:58:05 -07:00 |
|
tangxifan
|
7bcbd8a88b
|
[core] code format
|
2024-06-25 11:44:50 -07:00 |
|
tangxifan
|
3b2c13402a
|
[core] syntax
|
2024-06-25 11:44:25 -07:00 |
|
tangxifan
|
31d4b4c402
|
[core] now support add internal drivers to clock tree
|
2024-06-25 11:27:22 -07:00 |
|
tangxifan
|
66095322bb
|
Merge pull request #1728 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-25 09:42:34 -07:00 |
|
github-actions[bot]
|
ea5ab5117c
|
Updated Patch Count
|
2024-06-25 16:36:44 +00:00 |
|
tangxifan
|
fbfe3218c1
|
Merge pull request #1727 from lnis-uofu/dependabot/submodules/yosys-1288166
Bump yosys from `6c8ae44` to `1288166`
|
2024-06-25 09:36:25 -07:00 |
|
dependabot[bot]
|
4619e3ea53
|
Bump yosys from `6c8ae44` to `1288166`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `6c8ae44` to `1288166`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](6c8ae44ae7...1288166f7a)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-25 06:59:40 +00:00 |
|
tangxifan
|
272d78eb43
|
[test] add a new unit test
|
2024-06-24 19:13:36 -07:00 |
|
tangxifan
|
22bee35fd1
|
[lib] mem allocate
|
2024-06-24 18:47:56 -07:00 |
|
tangxifan
|
36ef555dda
|
[lib] add example arch for clock arch with internal drivers
|
2024-06-24 18:33:47 -07:00 |
|
tangxifan
|
2eda2825b7
|
[lib] syntax
|
2024-06-24 18:28:42 -07:00 |
|
tangxifan
|
0c442f6238
|
[lib] add syntax to support internal drivers in clock network parsers
|
2024-06-24 17:54:58 -07:00 |
|
tangxifan
|
428f5b4803
|
[ci] now use upload-artifact v4 due to deprecation
|
2024-06-24 15:23:55 -07:00 |
|
tangxifan
|
dd5c3dc769
|
[ci] use a new version of cancel-previous-flow due to node16 deprecation
|
2024-06-24 15:17:57 -07:00 |
|
tangxifan
|
582efc0501
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2
|
2024-06-24 10:42:29 -07:00 |
|
tangxifan
|
8f770a6e3c
|
Merge pull request #1725 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-24 10:37:07 -07:00 |
|
github-actions[bot]
|
a436afcc4f
|
Updated Patch Count
|
2024-06-24 17:21:57 +00:00 |
|
tangxifan
|
cd680fd21d
|
Merge pull request #1724 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-6a4f0ca
Bump vtr-verilog-to-routing from `2ff460a` to `6a4f0ca`
|
2024-06-24 10:21:36 -07:00 |
|
dependabot[bot]
|
9bdcc27913
|
Bump vtr-verilog-to-routing from `2ff460a` to `6a4f0ca`
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `2ff460a` to `6a4f0ca`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](2ff460a245...6a4f0cac3b)
---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-24 06:55:52 +00:00 |
|
tangxifan
|
253e3e0cba
|
[doc] add new syntax for clock network
|
2024-06-23 17:43:38 -07:00 |
|
tangxifan
|
9bb076d892
|
[test] fixed a bug on pin mapping of tetbenche
|
2024-06-21 20:29:21 -07:00 |
|
tangxifan
|
d2053db21c
|
[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
|
2024-06-21 19:00:01 -07:00 |