tangxifan
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c6246ae905
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[test] typo
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2024-08-09 17:10:51 -07:00 |
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tangxifan
|
38f1bdba4e
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[test] add a new test case
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2024-08-09 17:04:10 -07:00 |
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tangxifan
|
84c2b27c7b
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[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
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2024-08-02 17:24:44 -07:00 |
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tangxifan
|
c30eafac9f
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[test] fixed a bug on clk ntwk arch where some io clocks are not tapped
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2024-07-08 15:26:16 -07:00 |
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tangxifan
|
b50acacfba
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[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
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2024-07-08 15:09:31 -07:00 |
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tangxifan
|
6492d43a01
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[test] add a new test to validate perimeter cb using global tile clock
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2024-07-08 11:29:20 -07:00 |
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tangxifan
|
5c9c4d93c5
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[core] typo
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2024-07-08 10:46:47 -07:00 |
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tangxifan
|
ff56139a53
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[test] debugging
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2024-07-07 23:07:51 -07:00 |
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tangxifan
|
1a5e2392fc
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[test] add a new testcase to validate clock network when perimeter cb is on
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2024-07-07 22:32:13 -07:00 |
|
tangxifan
|
db12532eb8
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[test] typo
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2024-07-07 21:41:39 -07:00 |
|
tangxifan
|
a46820b7c1
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[core] add a new test for bottom-left tile grouping
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2024-07-05 18:00:37 -07:00 |
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tangxifan
|
a78fddc3cb
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[test] add a new testcase to validate perimeter cb
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2024-07-03 19:59:24 -07:00 |
|
tangxifan
|
29452a7442
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[test] fixed a bug on out-of-date arch
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2024-07-02 11:52:19 -07:00 |
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tangxifan
|
f25081eb31
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[test] add a new test to validate ecb when tile modules are used
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2024-05-20 21:10:49 -07:00 |
|
tangxifan
|
5f6050d404
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[test] add a new test to validate combo: group tile, tile annotation and subtile
|
2023-08-18 21:48:40 -07:00 |
|
tangxifan
|
e82e4f487e
|
[test] add a new test to validate io subtile support
|
2023-08-18 11:13:34 -07:00 |
|
tangxifan
|
667c5f8944
|
[test] fixed a bug on the testcase
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2023-07-27 22:02:28 -07:00 |
|
tangxifan
|
952e84fce1
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[test] now heterogeneous testcases for tile modules pass
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2023-07-27 20:30:32 -07:00 |
|
tangxifan
|
beaa687a20
|
[core] fixed bugs on supporting heterogeneous blocks in tile modules
|
2023-07-27 20:29:18 -07:00 |
|
tangxifan
|
65995d7c13
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
|
2023-07-27 17:03:02 -07:00 |
|
tangxifan
|
46e58a56cb
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[test] added a new test case to validate clock network when using the tile modules
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2023-07-27 16:39:48 -07:00 |
|
tangxifan
|
81d699a723
|
[test] added a new testcase to validate carry chain connections in tile modules
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2023-07-27 16:18:30 -07:00 |
|
tangxifan
|
e9f2adf3f9
|
[test] add a new testcase to validate carry chain connections when using tile modules
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2023-07-27 16:06:43 -07:00 |
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tangxifan
|
1ea8a33d4b
|
[test] add a new testcase to validate global tile connections on tile modules
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2023-07-27 15:57:38 -07:00 |
|
tangxifan
|
a2848940df
|
[test] add a new testcase to ease debugging
|
2023-07-26 22:32:03 -07:00 |
|
tangxifan
|
5685fbd5e8
|
[test] adding a new test case to validate the tile modules on 4x4 fabric
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2023-07-26 22:17:39 -07:00 |
|
tangxifan
|
0db4ef62e8
|
[test] add a new test for tile-based fabric: using preconfig testbenches
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2023-07-25 15:48:14 -07:00 |
|
tangxifan
|
82fe63297a
|
[test] add a new test for top-left tile grouping
|
2023-07-19 11:22:36 -07:00 |
|
tangxifan
|
8d02a6e600
|
[test] now testcases are using proper arch
|
2023-05-03 21:47:21 +08:00 |
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tangxifan
|
df771cb33a
|
[test] add a new testcase for subtile and deploy it to basic regression test
|
2023-05-03 15:41:29 +08:00 |
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
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tangxifan
|
0cb8457e21
|
[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
|
61376a2979
|
[Test] Add test cases for various tile organization
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2020-11-04 16:32:52 -07:00 |