Laboratory for Nano Integrated Systems (LNIS)
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73a4e1fafb
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Merge pull request #96 from LNIS-Projects/dev
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done…
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2020-09-26 13:16:47 -06:00 |
tangxifan
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154f23b108
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[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
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2020-09-26 11:54:06 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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c8d4be65e5
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Merge pull request #94 from LNIS-Projects/dev
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 22:28:24 -06:00 |
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tangxifan
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ffd926d686
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[Architecture] Update external bitstream
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2020-09-25 21:30:59 -06:00 |
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tangxifan
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dcbd6a0614
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[Architecture] Add lib name to TGATE to test compatibility
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2020-09-25 21:08:12 -06:00 |
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tangxifan
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1b4e449179
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[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
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2020-09-25 21:05:20 -06:00 |
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tangxifan
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6bea712db0
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[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 14:54:51 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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ad66f6c2f3
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Merge pull request #93 from LNIS-Projects/dev
[Architecture] Reorganize the cell netlists and update architecture f…
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2020-09-25 12:48:19 -06:00 |
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tangxifan
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019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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6262605556
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Merge pull request #92 from LNIS-Projects/dev
Smart Configuration Support and Verilog Netlist Refactoring
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2020-09-24 22:04:55 -06:00 |
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tangxifan
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20d6b2bf84
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[Architecture] Remove out-of-date Verilog testbench
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2020-09-24 21:14:13 -06:00 |
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tangxifan
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00bf775971
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[Architecture] Bug fix for adder renaming
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2020-09-24 20:54:18 -06:00 |
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tangxifan
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0a53a719bd
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[Architecture] Bug fix due to adder renaming
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2020-09-24 20:42:24 -06:00 |
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tangxifan
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e4bfa2ef51
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[Architecture] Update external bitstream file
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2020-09-24 20:16:50 -06:00 |
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tangxifan
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bd0f0144a0
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[Architecture] Rename AIB architecture for the new cell naming
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2020-09-24 20:14:16 -06:00 |
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tangxifan
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8edfc79f53
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[Architecture] Rename AIB cell
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2020-09-24 20:11:21 -06:00 |
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tangxifan
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4ada793c84
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[Architecture] Adapt openfpga architecture to follow the renamed adder cell
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2020-09-24 20:09:29 -06:00 |
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tangxifan
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53187044e6
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[Architecture] Rename adder cell
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2020-09-24 20:07:57 -06:00 |
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tangxifan
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4a0a448171
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[Architecture] Rename openfpga architecture for the I/O cell
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2020-09-24 19:56:01 -06:00 |
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tangxifan
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e0f9547f5b
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[Architecture] Rework the i/o cell Verilog HDL
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2020-09-24 19:53:54 -06:00 |
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tangxifan
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eb5fd1f44e
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[Architecture] Bug fix for architectures using scan-chain DFF cell
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2020-09-24 18:37:25 -06:00 |
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tangxifan
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60a14ccbd2
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[Architecture] Bug fix in architectures that use BRAM
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2020-09-24 18:20:55 -06:00 |
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tangxifan
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d51efd397f
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[Architecture] Bug fix for architectures using DFF cells
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2020-09-24 18:02:42 -06:00 |
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tangxifan
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3ade6d6ff5
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[Architecture] Bug fix for dff that are used in data path
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2020-09-24 17:53:30 -06:00 |
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tangxifan
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3e7c88eac8
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[Architecture] Bug fix in Verilog netlist for scan-chain DFF
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2020-09-24 17:41:03 -06:00 |
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tangxifan
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7494556316
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[Architecture] Bug fix for scan-chain FF cell
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2020-09-24 17:38:16 -06:00 |
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tangxifan
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54b3f244d3
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[Architecture] Remove obsolete Verilog netlists
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2020-09-24 17:35:02 -06:00 |
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tangxifan
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49d6863641
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[Architecture] Bug fix for scan-chain FF cell renaming
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2020-09-24 17:33:14 -06:00 |
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tangxifan
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0a5369f919
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[Architecture] Adapt all the architecture files to use standard DFF cell
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2020-09-24 17:26:48 -06:00 |
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tangxifan
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a30255b2a4
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[Regression Test] Deploy new test cases to CI
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2020-09-24 17:04:43 -06:00 |
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tangxifan
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19dd3778d9
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[Architecture] Add test case for memory bank to use both reset and set
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2020-09-24 17:04:24 -06:00 |
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tangxifan
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335f5b78c1
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[Regression Test] Add test case to use both set and reset for configuration frame
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2020-09-24 17:02:28 -06:00 |
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tangxifan
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2d81ff9012
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[Regression test] Add configuration chain test case where both set and reset are used
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2020-09-24 16:59:52 -06:00 |
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tangxifan
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fc154b8560
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[Architecture] Bug fix due to switching CCFF cell
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2020-09-24 16:45:56 -06:00 |
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tangxifan
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4d94fcb298
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[Regression Test] Bug fix in calling test cases
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2020-09-24 16:38:34 -06:00 |
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tangxifan
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8468f25b23
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[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
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2020-09-24 16:31:55 -06:00 |
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tangxifan
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79875d5a91
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[Architecture] Bug fix in the configuration chain arch using both reset and set
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2020-09-24 15:27:26 -06:00 |
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tangxifan
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9cb67e6097
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[Architecture] Now all the configuration chain architecture use the DFFR cell by default
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2020-09-24 15:19:37 -06:00 |
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tangxifan
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81965e75f6
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[Architecture] Bug fix in DFF Verilog HDL
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2020-09-24 14:53:21 -06:00 |
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tangxifan
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3b42fe94d6
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[Architecture] Update external bitstream file
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2020-09-24 14:41:44 -06:00 |
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tangxifan
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08838c4957
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[Regression Test] Deploy new configuration chain test cases to CI
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2020-09-24 14:36:39 -06:00 |
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tangxifan
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7fbccdd102
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[Regression Tests] Add test cases for configuration chain using different DFF cells
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2020-09-24 14:34:12 -06:00 |
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tangxifan
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178afb3c7f
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[Architecture] Add configuration chain architectures using different DFF cells
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2020-09-24 14:23:27 -06:00 |
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tangxifan
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98d88dc686
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[Architecture] Bug fix for vanilla memory organization
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2020-09-24 14:13:48 -06:00 |
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tangxifan
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efad0402c2
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[Regression Test] Bug fix for CI errors
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2020-09-24 13:55:41 -06:00 |
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tangxifan
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e7906899dd
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[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
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2020-09-24 13:53:12 -06:00 |
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tangxifan
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e832d806c7
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[Architecture] Add DFF Verilog netlist using standard naming convention
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2020-09-24 13:50:59 -06:00 |
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tangxifan
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1b13e8ecb1
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[Architecture] Bug fix in the SRAM Verilog
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2020-09-24 12:26:13 -06:00 |
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tangxifan
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9d9cf6ee71
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[Regression Test] Deploy new tests to CI
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2020-09-24 12:20:18 -06:00 |
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tangxifan
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ffd1a72d22
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[Architecture] Add regression tests for the frame-based configuration using reset and set signals
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2020-09-24 12:18:26 -06:00 |