Commit Graph

30 Commits

Author SHA1 Message Date
tangxifan 2ef083c49d adapt SB module builder to use bus ports 2020-06-30 16:02:40 -06:00
tangxifan 07e1979498 add architecture examples on wide memory blocks (width=2). tileable routing is working 2020-03-28 15:41:26 -06:00
tangxifan 610c71671f experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
2020-03-24 16:47:45 -06:00
tangxifan 8a996ceae5 bug fixed in tileable routing when heterogeneous blocks are considered;
VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
tangxifan ff474d87de fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs 2020-03-22 16:11:00 -06:00
tangxifan 3958ac2494 fix bugs in flow manager on default compress routing problems 2020-03-22 15:26:15 -06:00
tangxifan 9a518e8bb6 bug fixed for tileable rr_graph builder for more 4x4 fabrics 2020-03-21 18:07:00 -06:00
tangxifan 63c4669dbb fixed bug in the fast look-up for tileable rr_graph 2020-03-21 17:36:08 -06:00
tangxifan 28123b8052 remove the direct connected IPIN/OPIN from RR GSB builder 2020-03-21 11:38:39 -06:00
tangxifan 2ff2d65e58 start debugging tileable routing using larger array size. Bug spotted in finding chan nodes 2020-03-20 22:12:23 -06:00
tangxifan 3c37b33f17 critical bug fixed in edge sorting for rr_gsb 2020-03-20 17:45:50 -06:00
tangxifan 060c1a41d9 critical bug fixed for tileable routing: delayless and wire2ipin switch was reverted 2020-03-20 17:23:19 -06:00
tangxifan 708fda9606 fixed a bug in using tileable routing when directlist is enabled 2020-03-20 16:38:58 -06:00
tangxifan 7a7f8374b3 start deploying edge sorting in uniquifying SB modules 2020-03-08 15:24:34 -06:00
tangxifan 0fbf3fca41 start developing edge sorting inside RRGSB 2020-03-07 23:30:55 -07:00
tangxifan c36c302052 looks like tileable routing is working 2020-03-06 17:16:53 -07:00
tangxifan 245a379c4f start plug in tileable rr_graph builder 2020-03-06 16:03:00 -07:00
tangxifan 3eb59d201f adapt top function of tileable rr_graph builder 2020-03-06 15:24:26 -07:00
tangxifan 441a307100 add routing chan width corrector to rr_graph builder utils 2020-03-06 14:54:40 -07:00
tangxifan 441de12936 adapt Fc in gsb connection builder to use VPR8 Fc builder 2020-03-06 14:43:12 -07:00
tangxifan 8d350ee22f adapt tileable rr_graph edge builder to rr_graph object 2020-03-05 20:50:21 -07:00
tangxifan 328488f357 adapt chan rr node builder to use rr_graph obj 2020-03-05 20:15:16 -07:00
tangxifan 5067dd846e adapting channel rr_node builder for tileable rr_graph 2020-03-05 17:47:48 -07:00
tangxifan 850788eace adapt tileable rr_graph node builder for rr_graph object 2020-03-05 17:15:49 -07:00
tangxifan de62ce8872 add node builder for tileable rr_graph builder 2020-03-05 15:34:04 -07:00
tangxifan 646ee90937 bring tileable gsb builder for rr_graph online 2020-03-04 18:19:53 -07:00
tangxifan 4455615980 adapt tileable routing channel detail builder 2020-03-04 14:21:35 -07:00
tangxifan 6e83154703 move rr_gsb and rr_chan to tileable rr_graph builder 2020-03-04 14:14:28 -07:00
tangxifan 4b7d2221d1 adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr 2020-03-04 13:55:53 -07:00
tangxifan 524798799c start adapting tileable rr_graph builder. Bring channel node detail data structure online 2020-03-04 11:21:34 -07:00