Aram Kostanyan
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397f2e71f1
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Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
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2022-01-19 20:43:26 +05:00 |
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Aram Kostanyan
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bd158311c5
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Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
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2022-01-18 14:07:41 +05:00 |
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Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Awais Abbas
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598c5e6b75
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Test case for yosys-only flow added
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2022-01-14 15:37:47 +05:00 |
tangxifan
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824a03bdca
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[Flow] Patch new test case
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2022-01-02 20:20:36 -08:00 |
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tangxifan
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55da99f4ca
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[Flow] Add a new test case to validate DSP with registers
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2022-01-02 20:08:23 -08:00 |
nadeemyaseen-rs
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06fb4b0ece
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-25 00:00:22 +05:00 |
coolbreeze413
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31379062e3
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remove minor comments
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2021-11-18 18:40:15 +05:30 |
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nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
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coolbreeze413
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91094305bd
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enable all tests except 15 and 19
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2021-11-17 20:56:12 +05:30 |
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coolbreeze413
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840fa399c6
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enable single counter test (fails, needs debug)
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2021-11-09 21:36:33 +05:30 |
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Aram Kostanyan
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b332a5a1b4
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
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tangxifan
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ff264c00a2
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-31 11:51:34 -07:00 |
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tangxifan
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7f999d03c6
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[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
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2021-10-30 18:05:39 -07:00 |
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tangxifan
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370e3fef83
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[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
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2021-10-30 18:03:59 -07:00 |
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tangxifan
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c8e9dfbeda
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[Test] bug fix
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2021-10-30 16:50:57 -07:00 |
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tangxifan
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a4cfc84930
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[Test] Bug fix
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2021-10-30 16:00:47 -07:00 |
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tangxifan
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335347a74f
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[Test] Bug fix
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2021-10-30 15:48:25 -07:00 |
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tangxifan
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be47e78289
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[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
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tangxifan
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ad5cce0ae8
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[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
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2021-10-30 15:11:07 -07:00 |
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tangxifan
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40d11a45d9
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[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
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2021-10-30 14:49:56 -07:00 |
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tangxifan
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16de60e943
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[Test] Turn off ACE2 run in bitstream generation only flows
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2021-10-30 12:31:14 -07:00 |
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tangxifan
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b2c4e3314e
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[Test] Bug fix in test cases
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2021-10-11 10:28:09 -07:00 |
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tangxifan
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8566e2a0cd
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[Test] Renaming test case to follow naming convention as other fabric key test cases
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2021-10-11 09:56:23 -07:00 |
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tangxifan
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b8b02d37d5
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[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
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2021-10-11 09:53:23 -07:00 |
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tangxifan
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6122863548
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[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
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2021-10-09 20:44:28 -07:00 |
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tangxifan
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a1eaacf5a8
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[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
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2021-10-06 12:12:15 -07:00 |
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tangxifan
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b98a8ec718
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[Test] Added the dedicated test case for fixed shift register clock frequency
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2021-10-06 12:09:26 -07:00 |
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tangxifan
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189ade6c1e
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[Test] Bug fix
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2021-10-05 19:17:34 -07:00 |
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tangxifan
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f74ea5d39a
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[Test] Use the new openfpga shell script in don't care bit tests
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2021-10-05 19:14:44 -07:00 |
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tangxifan
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50604e4589
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[Test] move test cases
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2021-10-05 19:02:43 -07:00 |
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tangxifan
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fed6c133b1
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[Test] Add new tests to validate the correctness of bitstream files with don't care bits
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2021-10-05 18:59:33 -07:00 |
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tangxifan
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b21f212031
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[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
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2021-10-05 11:39:53 -07:00 |
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tangxifan
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52569f808e
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[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
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2021-10-05 10:57:33 -07:00 |
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tangxifan
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fa1908511d
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[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
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2021-10-04 16:36:20 -07:00 |
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tangxifan
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dda147e234
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[Flow] Add an example simulation setting file for defining programming shift register clocks
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2021-10-01 11:04:23 -07:00 |
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tangxifan
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89a97d83bd
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[Test] Added a new test case for the shift register banks in QuickLogic memory banks
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2021-09-29 16:28:06 -07:00 |
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tangxifan
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4400dae108
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[Test] Bug fix in the wrong arch name
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2021-09-28 11:40:25 -07:00 |
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tangxifan
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dae3554fd4
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[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
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2021-09-28 11:27:49 -07:00 |
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tangxifan
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655b195d8b
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[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
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2021-09-22 15:56:44 -07:00 |
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tangxifan
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b0aaab9c03
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[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
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2021-09-22 11:32:13 -07:00 |
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tangxifan
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abfa380333
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[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
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tangxifan
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51fc222d61
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[Test] Added a new test case for multi-region QL memory bank
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2021-09-22 10:01:33 -07:00 |
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tangxifan
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1412121541
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[Test] Added a new test to validate the fabric key parser for QL memory bank
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2021-09-21 16:20:24 -07:00 |
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tangxifan
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dc2d1d1c3c
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[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
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2021-09-21 15:42:20 -07:00 |
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tangxifan
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60fc3ab36c
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[Test] Added a new test case for the WLR memory bank
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2021-09-20 11:20:36 -07:00 |
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tangxifan
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b82cfdf555
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[Test] Add the QL memory bank test to regression test cases
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2021-09-09 09:29:21 -07:00 |
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tangxifan
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6adf439081
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Merge remote-tracking branch 'upstream/master'
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2021-09-01 14:19:00 -07:00 |
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tangxifan
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9f03ecb160
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[Test] Patch test case due to the changes in counter benchmarks
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2021-07-02 17:57:39 -06:00 |