tangxifan
|
3a5c26c6a1
|
[Test] Update IWLS test by using new architecture and customize DFF techmap
|
2021-04-21 19:51:25 -06:00 |
|
tangxifan
|
8cbea6a268
|
[HDL] Add technology library for customizable DFF synthesis
|
2021-04-21 19:50:51 -06:00 |
|
tangxifan
|
3d615e1516
|
[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
|
2021-04-21 19:50:07 -06:00 |
|
tangxifan
|
9d9840d9b7
|
[Arch] Add architecture using multi-mode DFFs
|
2021-04-21 19:49:48 -06:00 |
|
tangxifan
|
c198273378
|
Merge pull request #295 from lnis-uofu/multi_clock
Patches on multi-clock support in repacking stage
|
2021-04-21 15:22:53 -06:00 |
|
tangxifan
|
2e1cc5499d
|
[Doc] Add disclaimer for limitations when using repack pin constraints
|
2021-04-21 14:14:54 -06:00 |
|
tangxifan
|
8046b16c15
|
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
|
2021-04-21 14:04:34 -06:00 |
|
tangxifan
|
b203ef7bc2
|
[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
|
2021-04-21 14:03:51 -06:00 |
|
tangxifan
|
96ce6b545f
|
[Tool] Patch repack to consider design constraints for pins that are not equivalent
|
2021-04-21 13:53:08 -06:00 |
|
tangxifan
|
12f27cf117
|
Merge pull request #294 from lnis-uofu/mux_default_path
Support customizable default path in bitstream generation for any interconnect inside pb_type
|
2021-04-19 18:29:03 -06:00 |
|
tangxifan
|
2fa370d7d5
|
[Test] Patch regression tests for fpga bitstream
|
2021-04-19 17:15:14 -06:00 |
|
tangxifan
|
9b3dcc65bd
|
[Doc] Add new bitstream setting syntex 'interconnect' to documentation
|
2021-04-19 16:37:21 -06:00 |
|
tangxifan
|
17fb532ffa
|
Merge branch 'master' into mux_default_path
|
2021-04-19 16:23:44 -06:00 |
|
tangxifan
|
64163edbe6
|
[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
|
2021-04-19 16:15:25 -06:00 |
|
tangxifan
|
578d81b67a
|
[Test] Patch task configuration file
|
2021-04-19 16:15:00 -06:00 |
|
tangxifan
|
f7767ff4df
|
Merge pull request #284 from lnis-uofu/tutorials
Tutorials
|
2021-04-19 16:00:16 -06:00 |
|
tangxifan
|
18eb5c9de9
|
[Test] Deploy new test to CI
|
2021-04-19 15:56:41 -06:00 |
|
tangxifan
|
5976cc0a1c
|
[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
|
2021-04-19 15:54:18 -06:00 |
|
tangxifan
|
0aec30bac6
|
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
|
2021-04-19 15:53:33 -06:00 |
bbleaptrot
|
986ea492f6
|
Fix grammar line 38: lookup table ->Look-Up Table
|
2021-04-19 14:16:40 -06:00 |
|
tangxifan
|
5364b94cf8
|
[Tool] Update bitstream setting parser/writer to support interconnect-related syntax
|
2021-04-19 13:42:12 -06:00 |
|
tangxifan
|
2ff3dc0a0f
|
Merge branch 'master' into tutorials
|
2021-04-19 11:35:18 -06:00 |
|
bbleaptrot
|
bc6e9746c2
|
Fix more grammar mistakes
|
2021-04-19 09:48:42 -06:00 |
|
bbleaptrot
|
8431337f39
|
Fix grammar errors in fig captions and elsewhere
|
2021-04-19 09:36:13 -06:00 |
|
bbleaptrot
|
86c856d35a
|
Fix reference links
|
2021-04-19 09:25:54 -06:00 |
|
bbleaptrot
|
cd6beb5789
|
Add one more link to fabric_netlists
|
2021-04-19 09:14:47 -06:00 |
|
bbleaptrot
|
f8810940c3
|
Update links
|
2021-04-19 09:10:17 -06:00 |
|
bbleaptrot
|
fcb7ee3283
|
Update to properly reference fabric netlist page
|
2021-04-19 09:05:30 -06:00 |
|
bbleaptrot
|
5010fb1e7f
|
Update hyperlinks
|
2021-04-19 08:52:05 -06:00 |
|
bbleaptrot
|
291638ee0f
|
Trying to resolve hyperlink to right location
|
2021-04-19 08:45:02 -06:00 |
|
bbleaptrot
|
beed1ce31e
|
replace hyperlink with more stable :ref: link
|
2021-04-19 08:38:09 -06:00 |
|
tangxifan
|
e85402eaaa
|
Merge pull request #293 from lnis-uofu/dff_techmap
Enable correct reset stimuli in testbench generators
|
2021-04-18 17:15:28 -06:00 |
|
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
82dd09a180
|
Merge branch 'master' into dff_techmap
|
2021-04-18 12:09:52 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
0e65442afd
|
Merge pull request #292 from lnis-uofu/dff_techmap
Verilog testbench generator now accepts pin constraints on non-clock global ports
|
2021-04-17 23:02:35 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
253422e7b7
|
[Tool] Bugfix due to refactoring
|
2021-04-17 19:27:03 -06:00 |
|
tangxifan
|
02ca51d84b
|
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
|
2021-04-17 17:45:50 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
da619fabe7
|
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
|
2021-04-17 17:19:34 -06:00 |
|
tangxifan
|
03a709dce9
|
Merge branch 'master' into dff_techmap
|
2021-04-17 16:20:55 -06:00 |
|
tangxifan
|
6e1b58f8a6
|
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
|
2021-04-17 15:05:22 -06:00 |
|
tangxifan
|
7018073e28
|
[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
|
2021-04-17 15:04:51 -06:00 |
|
tangxifan
|
da95da933b
|
[Test] Add pin constraint file to map reset to correct FPGA pins
|
2021-04-17 15:04:26 -06:00 |
|
tangxifan
|
64b2700979
|
Merge branch 'master' into tutorials
|
2021-04-17 10:19:30 -06:00 |
|
tangxifan
|
8c5eb5e1d7
|
Merge pull request #291 from lnis-uofu/dff_techmap
Support DFF with asynchronous reset in tech mapping
|
2021-04-16 21:52:22 -06:00 |
|
tangxifan
|
e3dafe99da
|
[Arch] Revert to old version arch due to editing by mistake
|
2021-04-16 20:58:32 -06:00 |
|
tangxifan
|
c020333512
|
Merge branch 'master' into dff_techmap
|
2021-04-16 20:54:28 -06:00 |
|
tangxifan
|
7172fc9ea1
|
[Test] Patch test for architecture using asynchronous DFFs
|
2021-04-16 20:48:37 -06:00 |