tangxifan
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0a15f366cb
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[HDL] Patch dff models used in yosys tech map
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2021-04-16 20:48:15 -06:00 |
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tangxifan
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16e02ef485
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[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
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2021-04-16 20:47:39 -06:00 |
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tangxifan
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1c2f91b7e6
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[Script] Patch yosys script with dff tech map
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2021-04-16 20:47:18 -06:00 |
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tangxifan
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2666726f36
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[Script] Remove clock routing from example openfpga shell script without ace
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2021-04-16 20:46:49 -06:00 |
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tangxifan
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23d08757cf
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[Script] Add example script without using ACE2
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2021-04-16 20:20:10 -06:00 |
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tangxifan
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bbdc0e53af
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[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
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2021-04-16 20:14:48 -06:00 |
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tangxifan
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b11d03f9c5
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[Test] Deploy new test to CI
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2021-04-16 20:01:40 -06:00 |
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tangxifan
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93be81abe1
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[Test] Add test case for architecture using DFF with reset
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2021-04-16 20:00:48 -06:00 |
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tangxifan
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5414a6a3da
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[Script] Add yosys script with custom DFF tech mapping
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2021-04-16 20:00:30 -06:00 |
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tangxifan
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4239bb4e68
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[Arch] Patch architecture files using multi-mode DFFs
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2021-04-16 19:59:55 -06:00 |
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tangxifan
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f2f7f010ea
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[Arch] Add new architectures using DFF with reset in VPR
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2021-04-16 19:26:18 -06:00 |
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tangxifan
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64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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71df9700ea
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Merge pull request #290 from lnis-uofu/iwls2005
[WIP] Add opencore RTLs from IWLS 2005 benchmarks
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2021-04-16 17:41:05 -06:00 |
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tangxifan
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ff4460695b
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[HDL] Add dff tech map files for yosys
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2021-04-16 17:00:55 -06:00 |
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tangxifan
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e46c6e75a3
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[Benchmark] Add missing RTL for IWLS2005 benchmarks
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2021-04-16 16:50:41 -06:00 |
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tangxifan
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f395ed2718
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[Test] Deploy iwls tests to CI
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2021-04-16 16:13:46 -06:00 |
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tangxifan
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87587bbb74
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[Test] Add iwls2005 benchmarks to regression tests
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2021-04-16 16:12:05 -06:00 |
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tangxifan
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1566a5558a
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[Test] Add task configuration file for iwls2005
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2021-04-16 16:10:31 -06:00 |
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tangxifan
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43bf016576
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[Script] Add example openfpga shell script for iwls benchmark
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2021-04-16 16:09:47 -06:00 |
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tangxifan
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26d3b5a954
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[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
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2021-04-16 16:08:58 -06:00 |
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tangxifan
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86ad572530
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[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
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2021-04-16 14:27:54 -06:00 |
bbleaptrot
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410c6a12ff
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Update figures to be more accurate and clean
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2021-04-16 11:46:12 -06:00 |
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bbleaptrot
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221822f0f0
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update figures to correctly display out ports
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2021-04-16 11:33:01 -06:00 |
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bbleaptrot
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423d814730
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Update to include new figures
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2021-04-13 16:04:20 -06:00 |
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bbleaptrot
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eff784e77b
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Upload new figures for spypad tutorial
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2021-04-13 15:53:51 -06:00 |
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bbleaptrot
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46f60d0704
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Provide more explanation in Pre-Built Spypads
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2021-04-12 18:10:36 -06:00 |
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bbleaptrot
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0606479bf8
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Edit figures to better fit page
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2021-04-12 17:53:31 -06:00 |
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bbleaptrot
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bb5cd1de47
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Update to fix :numref: error example figure
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2021-04-12 17:09:16 -06:00 |
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bbleaptrot
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a0b01dccc7
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Update spypads_tutorial.rst to address comments
Add links to github OpenFPGA architecture files, reference fig_gpout_ports, instead of emphasize lines switch to numbering the important lines
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2021-04-12 17:02:56 -06:00 |
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bbleaptrot
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64e8e623a5
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Update to fix links to proper syntax
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2021-04-12 16:14:00 -06:00 |
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bbleaptrot
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bad49cdb75
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Update to change Spypads to spypads
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2021-04-12 16:07:38 -06:00 |
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bbleaptrot
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1744ce594e
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Rename Spypads_tutorial.rst to spypads_tutorial.rst
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2021-04-12 16:06:44 -06:00 |
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tangxifan
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6dea269018
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Merge branch 'master' into tutorials
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2021-04-12 15:10:25 -06:00 |
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bbleaptrot
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90df365259
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Fix a spacing issue on line 250
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2021-04-12 14:21:53 -06:00 |
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bbleaptrot
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198882da89
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Update link to From Verilog to Verification
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2021-04-12 14:20:40 -06:00 |
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bbleaptrot
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b176ca6c0c
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Update to improve readability
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2021-04-12 14:13:41 -06:00 |
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bbleaptrot
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a2c2b634e6
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Update link for _user_defined_template.v
This ensures it goes to the correct page after pull request 274 no longer works
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2021-04-12 14:00:54 -06:00 |
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bbleaptrot
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f626b17d04
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Update user_defined_temp_tutorial
Change "example" in the beginning of the page to "tutorial" for clarity
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2021-04-12 13:58:19 -06:00 |
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tangxifan
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0cfea2f73c
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Merge pull request #287 from lnis-uofu/fpga_sdc_test
Enriched FPGA-SDC regression tests by sweeping time units
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2021-04-11 21:52:20 -06:00 |
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tangxifan
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b469705819
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Merge branch 'master' into fpga_sdc_test
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2021-04-11 21:14:46 -06:00 |
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tangxifan
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1db8bd7eec
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[Test] Update regression test with new SDC tests
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2021-04-11 20:24:32 -06:00 |
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tangxifan
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07f6066c11
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[Script] Update timing unit in SDC example script
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2021-04-11 20:24:18 -06:00 |
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tangxifan
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94c4c817eb
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[Test] Expand sdc time unit test to sweep all the available units
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2021-04-11 20:14:09 -06:00 |
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tangxifan
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c9f27ec4c2
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Merge pull request #286 from lnis-uofu/generate_testbench_test
Update generate_fabric and generate_testbench test cases
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2021-04-11 18:05:20 -06:00 |
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tangxifan
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a4893e27cf
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[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
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2021-04-11 17:26:27 -06:00 |
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tangxifan
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9b7001bc0f
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Merge branch 'master' into tutorials
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2021-04-10 17:16:09 -06:00 |
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tangxifan
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b4c03bce49
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Merge pull request #285 from lnis-uofu/fabric_bitstream_writer
Fabric bitstream writer supports multiple regions
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2021-04-10 16:41:38 -06:00 |
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tangxifan
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e5b47b7d3d
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[Doc] Update documentation on the changes on fabric bitstream file formats
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2021-04-10 15:45:39 -06:00 |
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tangxifan
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7c6e000be8
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[Tool] bug fix
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2021-04-10 15:36:02 -06:00 |
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tangxifan
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03b68a1fdd
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[Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions
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2021-04-10 15:25:39 -06:00 |