4cc8b08a6c
[Tool] Add openfpga version display
2021-01-23 16:38:00 -07:00
0670c2de59
[Tool] Deploy pin constraints to preconfig Verilog module generation
2021-01-19 16:56:30 -07:00
bb8e7e25c2
[Tool] Start deploying design constraints in repack engine
2021-01-16 21:27:12 -07:00
fa67517349
[Tool] Add repack design constraints to openfpga command 'repack'
2021-01-16 18:49:34 -07:00
87b2c1f3b8
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
2021-01-15 12:01:53 -07:00
852f5bb72e
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
2021-01-14 15:38:24 -07:00
cc91a0aebd
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
2021-01-04 17:14:26 -07:00
6bdfcb0147
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
2020-12-05 12:44:09 -07:00
6f18688f0e
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
2020-12-05 10:53:01 -07:00
5be9e9b736
[Tool] Adapted tools to support I/O in center grid
2020-12-04 18:50:13 -07:00
73aaa261d8
[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
2020-12-04 17:55:25 -07:00
b661c39b04
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
2020-12-02 19:36:36 -07:00
57a24570f5
[Tool] Move icarus and signal initialization options to testbench generator
2020-11-22 16:01:31 -07:00
372fb261fd
[Tool] Extend the support on global tile port for I/O tiles
2020-11-11 15:09:40 -07:00
9cbc374b33
[Tool] Add check codes for tile annotation
2020-11-11 12:03:13 -07:00
81e56d45d6
[Tool] Update FPGA-SDC to use the new data structure for global ports
2020-11-10 21:17:17 -07:00
c61ec5a8b8
[Tool] Bug fix for defining global ports from tiles
2020-11-10 20:31:14 -07:00
dcb50e4f19
[Tool] Use use standard data structure to store global port information
2020-11-10 19:07:28 -07:00
e4d974c5c8
[Tool] Split io location mapping builder from fabric builder
2020-11-02 18:27:34 -07:00
1ef0898f41
[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
2020-10-12 12:31:51 -06:00
721bcce373
[Tool] Change analysis SDC file name to track netlist name
2020-10-10 17:43:35 -06:00
e179a58b15
[OpenFPGA Tool] Bug fix for long runtime
2020-09-28 20:42:18 -06:00
064678fe32
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
2020-09-23 20:27:52 -06:00
1dfb3e06cc
[FPGA-SPICE] add SPICE writer for logic blocks
2020-09-20 12:38:24 -06:00
5e78e91fdf
[FPGA-SPICE] Add SPICE writer for routing blocks
2020-09-20 12:27:48 -06:00
0f9fce92b2
[FPGA-SPICE] Add SPICE writer for routing multiplexers
2020-09-20 11:49:02 -06:00
9cfb2f52ef
[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
2020-09-16 19:26:46 -06:00
fc6bfdc7a2
[OpenFPGA Code] Patch syntax compatibility for older gcc
2020-09-14 18:55:21 -06:00
5d83abb2cf
bug fix in read architecture bitstream and regression tests
2020-07-27 19:37:05 -06:00
6592db3dfe
bug fix in calling the wrong function of write_fabric_bitstream
2020-07-27 14:32:58 -06:00
d68e77f322
Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
2020-07-27 14:16:33 -06:00
5fb7d9fbdb
bug fix in fabric bitstream file format writer
2020-07-26 21:28:45 -06:00
92d2d2d849
add fabric bitstream XML writer
2020-07-26 21:00:57 -06:00
2603836111
split logical tile netlists to keep good Verilog hierarchy
2020-07-24 12:53:21 -06:00
be5966475e
formulate file name, module name and instance name to be consistent
2020-07-24 12:23:27 -06:00
b5fd6aa859
add inverter subckt writer to FPGA-SPICE
2020-07-17 13:01:08 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
462fc0d04e
add spice transistor wrapper writer
2020-07-05 14:50:29 -06:00
81171a8f97
start transplanting FPGA-SPICE
2020-07-05 12:10:12 -06:00
1f38e17111
bug fix for naming conflicts in mux local encoder and architecture decoders
2020-07-03 14:12:13 -06:00
adee87569d
enable fast bitstream building by creating a frame view of fabric
2020-07-02 16:25:36 -06:00
0a3c746fb1
now split CB module bus ports into lower/upper parts
2020-07-01 14:37:13 -06:00
e688ca1388
update fabric bitstream writer to support various configuration protocols
2020-07-01 11:54:28 -06:00
2e7684b746
adapt bus ports in connection block module builder
2020-06-30 17:50:53 -06:00
2ef083c49d
adapt SB module builder to use bus ports
2020-06-30 16:02:40 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
aded675633
rename files in fpga bitstream library to be consistent with conventions
2020-06-21 13:06:39 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
tangxifan