Xifan Tang
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b4542ea34b
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minor fix on doc about the global and general purpose port
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2020-04-09 17:10:04 -06:00 |
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Xifan Tang
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d99776b260
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update documentation on the global I/O ports
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2020-04-08 18:18:53 -06:00 |
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Xifan Tang
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55e68896d6
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doc update for the support on std cell MUX2 and examples
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2020-04-07 12:01:13 -06:00 |
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Xifan Tang
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7a4137fdcf
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doc update for packable XML syntax in VPR
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2020-04-06 18:37:05 -06:00 |
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Xifan Tang
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1a3a748dd2
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update documentation with the support on spypads and global I/O ports
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2020-04-05 20:12:28 -06:00 |
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Xifan Tang
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fd8248d9dd
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update documentation: the addon syntax on VPR and configuration protocols
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2020-04-01 12:35:52 -06:00 |
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tangxifan
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78964ce71c
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update documentation on the through channel
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2020-03-27 11:34:39 -06:00 |
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Xifan Tang
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b4221e94bb
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add documentation on the tileable routing and thru channel support
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2020-03-25 16:52:42 -06:00 |
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tangxifan
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1d766d2a70
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minor format fix on documentation
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2020-03-11 10:22:30 -06:00 |
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tangxifan
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089cc5e86e
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update documentation on circuit model annotation on VPR architecture
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2020-03-10 16:51:50 -06:00 |
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tangxifan
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7195564455
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reworked circuit model examples in documentation. Now we are consistent to latest syntax
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2020-03-10 16:17:20 -06:00 |
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tangxifan
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54dfdc0cc1
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update general documentation on circuit library
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2020-03-10 12:18:12 -06:00 |
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tangxifan
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2a3c5b98a5
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minor format fix in documentation
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2020-03-09 21:25:13 -06:00 |
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Xifan Tang
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d14fa16905
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finish documentation update on technology library
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2020-03-09 21:17:25 -06:00 |
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Xifan Tang
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cb7e4a1dfa
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finish documentation the simulation settings in VPR8 integration
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2020-03-09 20:03:37 -06:00 |
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tangxifan
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751735bf41
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update documentation in simulation setting syntax
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2020-03-09 17:40:33 -06:00 |
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tangxifan
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f67981afa8
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update ducoumentation to explain lib_name XML syntax
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2020-01-08 14:22:17 -07:00 |
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tangxifan
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323c4fdc9a
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clean up documentation build warnings and add guidelines for port naming
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2019-12-04 11:59:10 -07:00 |
AurelienUoU
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36f7624b95
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Point to point truth table typo fix
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2019-10-01 13:07:27 -06:00 |
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AurelienUoU
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e2867019e1
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Typo fixing
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2019-09-30 10:38:02 -06:00 |
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AurelienUoU
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74f7a3cfb2
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Doc fixing
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2019-09-30 10:29:42 -06:00 |
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AurelienUoU
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5ac79f4805
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Point to point documentation
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2019-09-30 10:00:46 -06:00 |
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tangxifan
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42b528be57
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doc updates
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2019-08-21 15:11:25 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
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b207050b03
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minor fix in documentation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
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fc93a4941a
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update documentation
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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7603850d72
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complete documentation for new features
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2019-08-06 14:17:56 -06:00 |
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tangxifan
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8a046394f8
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add documentation for multi-mode configurable block support
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2019-07-30 16:47:41 -06:00 |
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Xifan Tang
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e7b40f06b0
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Add documentation for fracturable LUTs
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2019-07-17 15:21:07 -04:00 |
BaudouinChauviere
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f4b72bd4e1
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Update link_circuit_modules.rst
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2019-04-01 16:21:59 -06:00 |
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BaudouinChauviere
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ce300c196c
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Update circuit_modules.rst
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2019-04-01 16:13:23 -06:00 |
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BaudouinChauviere
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6e065ef3b3
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Update tech_lib.rst
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2019-04-01 16:09:31 -06:00 |
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BaudouinChauviere
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aed779ca3d
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Update spice_sim_setting.rst
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2019-04-01 16:08:00 -06:00 |
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BaudouinChauviere
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4900caaed9
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Update generality.rst
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2019-04-01 16:04:17 -06:00 |
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BaudouinChauviere
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10cbd2efef
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Update index.rst
Commenting the multi mode out until more mature
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2018-12-03 11:50:13 -07:00 |
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BaudouinChauviere
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8e7def7f88
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Update link_circuit_modules.rst
Correction of typos
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2018-12-03 11:39:44 -07:00 |
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BaudouinChauviere
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a4d29aeb1b
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Update circuit_model_examples.rst
Typo correction
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2018-12-03 11:26:04 -07:00 |
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BaudouinChauviere
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e39e0219e9
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Update circuit_modules.rst
Move the examples from this part to their own
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2018-12-03 10:59:20 -07:00 |
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BaudouinChauviere
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7a49ca8ce2
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Update index.rst
New section in the doc
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2018-12-03 10:58:50 -07:00 |
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BaudouinChauviere
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99769c1510
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Create circuit_model_examples.rst
Better architecture of the doc
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2018-12-03 10:58:11 -07:00 |
Aurelien Alacchi
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4a950c6857
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Flatten_hierarchy_doc
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2018-10-18 16:28:12 -06:00 |
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Aurelien Alacchi
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e0c2fc2c8a
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Documentation_code&example_update
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2018-10-12 15:50:09 -06:00 |
Aurelien Alacchi
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07380ed1fa
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Minor_bug_fig_name_correction
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2018-10-09 15:33:30 -06:00 |
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Aurelien Alacchi
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a43574e593
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Update_doc_circuit_level_fig_fixed
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2018-10-09 15:29:15 -06:00 |
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Aurelien Alacchi
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d1c01cd68b
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Update_bug_fig_doc_CL
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2018-10-08 17:54:44 -06:00 |
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Aurelien Alacchi
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7c51129a33
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test42docFig
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2018-10-08 16:20:34 -06:00 |
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Aurelien Alacchi
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8723722e99
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test_correction_bug_fig_doc_CL
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2018-10-08 16:18:56 -06:00 |
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Aurelien Alacchi
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ebd4b282f5
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test_correction_figure
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2018-10-08 16:00:21 -06:00 |
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Aurelien Alacchi
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a318f8e20e
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Update_doc_circuit_level_bug_image
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2018-10-08 15:48:54 -06:00 |
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Aurelien Alacchi
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f79913f379
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Update_doc_circuit_level_bug_image
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2018-10-08 15:42:19 -06:00 |