tangxifan
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28b7a12f68
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[core] code format
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2023-04-23 14:31:35 +08:00 |
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tangxifan
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bd511ba515
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[core] fixed syntax errors
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2023-04-23 14:26:08 +08:00 |
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tangxifan
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592765af48
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[core] code complete for upgrading netlist generator w.r.t. ccff v2
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2023-04-23 13:57:37 +08:00 |
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tangxifan
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46510388be
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[core] now fabric generator can wire clock ports to routing blocks
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2023-03-02 12:33:26 -08:00 |
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tangxifan
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974263f0fa
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[core] dev
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2023-03-01 23:27:29 -08:00 |
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tangxifan
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099d9f32f4
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[core] dev
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2023-03-01 16:08:15 -08:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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0c2b49ddb9
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[engine] remove debugging log output
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2022-08-27 13:06:05 -07:00 |
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tangxifan
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b3e4a06969
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[engine] adapt vpr wrapper to the latest main.cpp from vtr
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2022-08-23 14:28:05 -07:00 |
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tangxifan
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0a6b794ef0
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[engine] fixed bugs in subtiles. Revisited the usage of client functions
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2022-08-23 12:35:04 -07:00 |
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tangxifan
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019e663e12
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[engine] fixing the bugs on building global nets to sub tile pins
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2022-08-23 11:58:44 -07:00 |
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tangxifan
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e0ae851e28
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[engine] correcting compilation errors due to vpr upgrade
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2022-08-17 16:25:12 -07:00 |
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tangxifan
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0c329866da
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[engine] Use RRGraphView in openfpga source codes
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2022-08-16 16:48:32 -07:00 |
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tangxifan
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4d67864c2c
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[Engine] Now global port can be connected partial pins of a tile port
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2022-03-20 11:36:03 +08:00 |
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tangxifan
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cbbf601edc
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[Tool] Fix a compiler warning due to uninitialized data structure
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2021-06-18 16:20:13 -06:00 |
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tangxifan
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c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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tangxifan
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956b9aca01
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[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
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tangxifan
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2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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tangxifan
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c0da6b900a
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[Tool] Bug fix in creating multi-bit clock port connections
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2021-01-12 18:38:00 -07:00 |
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tangxifan
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65b2fe3ab7
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[Tool] Bug fix in the global tile connection by considering all the subtiles
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2021-01-10 11:52:38 -07:00 |
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tangxifan
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9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
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372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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tangxifan
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9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
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cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
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81ecfa3197
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add comments to clarify how to select CB ports when connecting to SBs at the top level
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2020-07-01 14:44:40 -06:00 |
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tangxifan
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0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
|
2e7684b746
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adapt bus ports in connection block module builder
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2020-06-30 17:50:53 -06:00 |
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tangxifan
|
2ef083c49d
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adapt SB module builder to use bus ports
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2020-06-30 16:02:40 -06:00 |
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tangxifan
|
025d4a3599
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use efficient net builder in top module connection builder
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2020-06-29 23:28:26 -06:00 |
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tangxifan
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e7d5736269
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add profile time to top module builder for better spot on runtime/memory overhead sources
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2020-06-29 23:17:03 -06:00 |
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tangxifan
|
4bf0a63ae6
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bug fixed for multiple io types defined in FPGA architectures
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2020-03-27 16:32:15 -06:00 |
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tangxifan
|
b6bdf78d95
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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tangxifan
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fc6abc13fd
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add physical tile utils to identify pins that have Fc=0
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2020-03-21 21:02:47 -06:00 |
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tangxifan
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9dc9c2c9f7
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add build top module connection functions
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2020-02-14 10:45:24 -07:00 |