tangxifan
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79b260f5e1
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[arch] update missing arch
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2022-09-21 16:52:32 -07:00 |
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tangxifan
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b1f8cdab3c
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[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
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2022-09-21 15:28:56 -07:00 |
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tangxifan
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eaa0b5588a
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[test] fixed a bug in pin constrain examples
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2022-09-21 14:10:12 -07:00 |
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tangxifan
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b532bca9d2
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[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
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2022-09-21 10:54:16 -07:00 |
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tangxifan
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baac236ed7
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[test] fixed a bug in example scripts due to the changes on vpr options
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2022-09-21 10:52:49 -07:00 |
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tangxifan
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d0b018ad6e
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[script] mismatches in vpr options due to upgrade
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2022-09-21 09:27:26 -07:00 |
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tangxifan
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40edf859e3
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Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-20 22:38:06 -07:00 |
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tangxifan
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97f0445787
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[arch] upgrade arch file which was designed for v1.1
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2022-09-20 22:37:35 -07:00 |
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tangxifan
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36603f9772
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Merge branch 'master' into vtr_upgrade
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2022-09-20 21:08:06 -07:00 |
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tangxifan
|
e0f632cc9c
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[test] fixed a bug
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2022-09-20 20:29:34 -07:00 |
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tangxifan
|
645d8df7b9
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[test] fixed a bug
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2022-09-20 20:09:41 -07:00 |
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tangxifan
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9042fc2422
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[test] now reg test should show diff details when failed
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2022-09-20 19:32:34 -07:00 |
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tangxifan
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b8f1520367
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[test] fixed a bug
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2022-09-20 18:12:23 -07:00 |
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tangxifan
|
4e254a304d
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[test] now golden netlists have no relationship with OPENFPGA_PATH
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2022-09-20 18:10:52 -07:00 |
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tangxifan
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5e23be19a5
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[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
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2022-09-20 18:07:31 -07:00 |
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tangxifan
|
1b0b50b928
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[test] update golden netlist
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2022-09-20 16:04:05 -07:00 |
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tangxifan
|
a137f7148c
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[arch] fixed a bug
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2022-09-20 15:47:15 -07:00 |
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tangxifan
|
da157ed5de
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[test] debugging git-diff
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2022-09-20 15:31:39 -07:00 |
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tangxifan
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3f8106f12e
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[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
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2022-09-20 15:19:32 -07:00 |
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tangxifan
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b630d60b7e
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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
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2022-09-20 14:14:18 -07:00 |
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tangxifan
|
6a896a9845
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[test] debugging
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2022-09-20 14:08:22 -07:00 |
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tangxifan
|
ecfdc4a83a
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[test] debugging
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2022-09-20 13:51:32 -07:00 |
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tangxifan
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abee802830
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[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
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2022-09-20 13:46:30 -07:00 |
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tangxifan
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bdcdc7d294
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[test] Now git diff in basic regression tests should capture the changes on golden outputs
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2022-09-20 13:36:31 -07:00 |
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tangxifan
|
37c5056d6a
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[test] now use a fixed routing channel width for quicklogic tests
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2022-09-20 12:25:40 -07:00 |
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tangxifan
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846ca26311
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[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
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2022-09-20 12:08:24 -07:00 |
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tangxifan
|
b3449a338f
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[arch] update out-of-date vpr arch from v1.1 to v1.2
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2022-09-20 09:51:43 -07:00 |
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tangxifan
|
63cb8d589d
|
[test] fixed a typo
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2022-09-19 23:14:15 -07:00 |
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tangxifan
|
40663f956c
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[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
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2022-09-19 21:55:15 -07:00 |
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tangxifan
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d9bd0a6cf3
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[test] disable clustering-routing result sync-up when calling vpr in example scripts
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2022-09-19 20:52:04 -07:00 |
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tangxifan
|
fca1c82388
|
[test] disable clustering and routing sync when using VPR
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2022-09-19 20:33:35 -07:00 |
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tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
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tangxifan
|
a8d7b6c2c4
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[script] add a python script for users to visualize the I/O sequence
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2022-09-16 10:49:10 -07:00 |
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tangxifan
|
a2e22787c2
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[test] deploy the new test cases to the basic regression tests
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2022-09-16 10:31:15 -07:00 |
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tangxifan
|
10e86d334a
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[test] add test cases to validate the various layouts where I/Os are in the center of the grid
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2022-09-16 10:29:19 -07:00 |
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tangxifan
|
f2e13e5ea9
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[arch] add more flexible layout to test I/O center features
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2022-09-16 10:00:08 -07:00 |
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tangxifan
|
ec38b3990f
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[arch] update to check OpenFPGA I/O indexing
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2022-09-14 13:58:12 -07:00 |
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tangxifan
|
83c89ae1bf
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[arch] add more corner case to test the custom I/O location feature
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2022-09-13 23:05:41 -07:00 |
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tangxifan
|
330785635d
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[test] now use a bigger fabric for the test case on custom I/O location
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2022-09-13 17:53:33 -07:00 |
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tangxifan
|
a37e270f25
|
[arch] now custom I/O loc test case cover I/Os in the center of the fabric
|
2022-09-13 16:57:18 -07:00 |
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tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |
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tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
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tangxifan
|
a3d070ac6f
|
[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
|
2022-09-12 10:43:21 -07:00 |
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tangxifan
|
314f5395b4
|
[benchmark] fixed a bug which causes yosys failed
|
2022-09-09 17:04:59 -07:00 |
|
tangxifan
|
91fe27ff66
|
[test] deploy new test to ci
|
2022-09-09 17:00:28 -07:00 |
|
tangxifan
|
1ab7590603
|
[test] added a new test case to
|
2022-09-09 16:59:06 -07:00 |
|
tangxifan
|
cc974a80f7
|
[arch] added a new architecture to test the local routing architecture where reset is on LUT
|
2022-09-09 16:48:10 -07:00 |
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tangxifan
|
7a38c7dd18
|
[benchmark] add a new benchmark to test reset signal to drive both lut and ff
|
2022-09-09 16:42:55 -07:00 |
|
tangxifan
|
95d7a17b3c
|
Merge branch 'master' into vtr_upgrade
|
2022-09-09 14:32:42 -07:00 |
|
tangxifan
|
d4523e819c
|
[test] fixed a bug
|
2022-09-08 16:55:50 -07:00 |