github-actions[bot]
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0a849373d1
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Updated Patch Count
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2022-02-21 00:02:22 +00:00 |
tangxifan
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f430427669
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Merge pull request #542 from lnis-uofu/bus_support
More tests on Bus support: Validate its correctness on Input buses
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2022-02-20 11:37:48 -08:00 |
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tangxifan
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e33ba667e4
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[Test] Add missing file
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2022-02-20 10:59:44 -08:00 |
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tangxifan
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f30de1085c
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[Test] Cover all the related testcase about bus group
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2022-02-19 23:33:16 -08:00 |
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tangxifan
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b4202f52b4
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[Test] debugging
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2022-02-19 23:26:29 -08:00 |
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tangxifan
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785bb1633d
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[Test] trying to see if we support busgroup per benchmark in task configuration file
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2022-02-19 23:23:36 -08:00 |
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tangxifan
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cfd4b6f2bf
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Merge pull request #541 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-02-19 16:38:44 -08:00 |
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github-actions[bot]
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4ca45791a4
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Updated Patch Count
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2022-02-20 00:02:56 +00:00 |
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tangxifan
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756c340232
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Merge pull request #540 from lnis-uofu/bus_support
Bus support now support big-endian and little-endian
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2022-02-19 10:23:27 -08:00 |
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tangxifan
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1c18d14ad5
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[FPGA-Verilog] Add big/little endian support to output ports
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2022-02-19 09:23:48 -08:00 |
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tangxifan
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3e43a60fdc
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[FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks
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2022-02-19 09:15:38 -08:00 |
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tangxifan
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7645d5332d
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[Test] Update bug group examples on the big endian support
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2022-02-18 23:09:03 -08:00 |
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tangxifan
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b78e58d9bf
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[Doc] Update doc about big endian syntax in bus group file format
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2022-02-18 23:07:18 -08:00 |
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tangxifan
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671188dfa4
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[FPGA-Verilog] Now support big/little-endian in bus group
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2022-02-18 23:05:03 -08:00 |
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tangxifan
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feaaeea787
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Merge pull request #539 from lnis-uofu/bus_support
Support buses in Verilog testbenches
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2022-02-18 16:48:52 -08:00 |
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tangxifan
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a78d091606
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Merge branch 'master' into bus_support
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2022-02-18 15:51:03 -08:00 |
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tangxifan
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8116141210
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[Doc] Update documentation on the bus group feature
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2022-02-18 15:46:25 -08:00 |
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tangxifan
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68644ea0f6
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[Test] Add the new test to basic regression tests
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2022-02-18 15:44:07 -08:00 |
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tangxifan
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f0ce1e79a3
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[Test] Added a new test to validate bus group in full testbench
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2022-02-18 15:43:21 -08:00 |
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tangxifan
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790715f46a
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[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator
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2022-02-18 15:41:35 -08:00 |
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tangxifan
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fe9e0ff977
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[Test] Add the new test to basic regression tests
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2022-02-18 15:38:53 -08:00 |
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tangxifan
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c897a64ad5
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[Script] Add a new example script to test full testbenches using bus group features
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2022-02-18 15:37:42 -08:00 |
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tangxifan
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223575cf3e
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[Test] Added a new test for bus group on full testbenches
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2022-02-18 15:33:29 -08:00 |
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tangxifan
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85c893c94c
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[Test] Add new test to basic regression tests
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2022-02-18 15:30:08 -08:00 |
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tangxifan
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5ab84e1861
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[Test] Add a new test for bus group
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2022-02-18 15:29:33 -08:00 |
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tangxifan
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b4d59fdd1e
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[Test] Update bus group file due to little and big endian conversion during yosys/vpr
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2022-02-18 15:02:08 -08:00 |
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tangxifan
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36543f7f2f
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[Script] Support simplified rewriting for Yosys on output verilog
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2022-02-18 14:54:39 -08:00 |
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tangxifan
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401f673f16
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[FPGA-Verilog] Streamline codes by using APIs
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2022-02-18 14:47:36 -08:00 |
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tangxifan
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c16ea8d082
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[FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches
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2022-02-18 14:34:32 -08:00 |
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tangxifan
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a4dc86a33d
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[FPGA-Verilog] Now output atom block name removal has a dedicated function
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2022-02-18 14:30:46 -08:00 |
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tangxifan
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f5dd89bbd9
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[FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used
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2022-02-18 14:08:03 -08:00 |
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tangxifan
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8ba3d06392
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[Test] Fixed bugs in simulation settings
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2022-02-18 12:36:22 -08:00 |
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tangxifan
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94fea84a40
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[Lib] Fix a bug in memory allocation
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2022-02-18 12:36:03 -08:00 |
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tangxifan
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a4d5172b7c
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[Test] Fixed bugs that causes VPR failed
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2022-02-18 12:31:29 -08:00 |
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tangxifan
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43d852d8a1
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[Test] Add the bus group test case to basic regression tests
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2022-02-18 12:27:25 -08:00 |
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tangxifan
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7176037bc4
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[Test] Added a new test about bus group
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2022-02-18 12:26:00 -08:00 |
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tangxifan
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73e6ee964d
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[Script] Add a new example script showing how to use bus group features
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2022-02-18 12:25:34 -08:00 |
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tangxifan
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0d620888ab
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[FPGA-Verilog] Now instance can output bus ports with all the pins
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2022-02-18 12:03:26 -08:00 |
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tangxifan
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aa375fd7a4
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[FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator
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2022-02-18 11:31:11 -08:00 |
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tangxifan
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6da0ede9b0
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[FPGA-Verilog] Adding bus group support to all Verilog testbench generators
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2022-02-17 23:48:44 -08:00 |
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tangxifan
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c96f0d199d
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[FPGA-Verilog] Adding bus group support in Verilog testbenches
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2022-02-17 23:14:28 -08:00 |
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tangxifan
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37d8617a5c
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[Doc] Update due to new options
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2022-02-17 19:45:37 -08:00 |
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tangxifan
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38601f325b
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[Engine] Add bus group to OpenFPGA core
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2022-02-17 17:28:55 -08:00 |
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tangxifan
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e60d7d12b7
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[Lib] Fixed a bug in writer
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2022-02-17 17:12:07 -08:00 |
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tangxifan
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4b3f906f11
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[Lib] Fixed all the syntax errors
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2022-02-17 17:09:03 -08:00 |
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tangxifan
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8d4087f893
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Merge pull request #538 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2022-02-17 16:28:09 -08:00 |
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github-actions[bot]
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0a6421a1fc
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Updated Patch Count
|
2022-02-18 00:24:29 +00:00 |
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tangxifan
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27627bf5b4
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[Lib] Add an example XML for bus group unit tests
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2022-02-17 16:22:01 -08:00 |
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tangxifan
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0d7e949166
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[Lib] Add unit test for bus group
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2022-02-17 16:21:12 -08:00 |
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tangxifan
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76cf4e1662
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[Lib] Add reader and writer for bus group
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2022-02-17 16:17:37 -08:00 |