tangxifan
|
47f040822f
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deploy the tests to CI
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
4083fae41a
|
add new test cases about user-defined simulation settings
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
2fbf9c2cfc
|
change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
0e44cf3ea3
|
now SDC to disable routing multiplexer outputs can use wildcards
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2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
609115e51f
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now hierarchical SDC generation is applicable to CB timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
d18e924a89
|
Update documentation on new fpga_sdc option
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7e82c23f52
|
now add SDC generator supports both hierarchical and flatten in writing timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7503c58fb2
|
small fix on SDC generator for SB which do not exist in FPGA
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
d0793d9029
|
now disable_sb_output support wildcard
|
2020-06-11 19:31:02 -06:00 |
|
Xifan Tang
|
ecdbdcb592
|
update documentation on new SDC options
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
8695c5ee78
|
add options to use general-purpose wildcards in SDC generator
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
facd87dafe
|
use wildcard in SDC generation for multiple-instanced-blocks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
1e2226e1c3
|
now use explicit port mapping in the verilog testbenches for reference benchmarks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
889bc8dbe8
|
add more test cases about LUT design and deploy to CI
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
1d35ac8086
|
deploy local encoder to CI
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
889f179ce7
|
add local encoder test case
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
98a658a013
|
bug fixed in routing_test.v. Deployed to regression tests
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
6dd8d347e1
|
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
|
2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
|
f6cea1e17c
|
Added test_mode_low benchmark
|
2020-06-11 19:31:01 -06:00 |
|
CHARAS SAMY
|
3c781b18d3
|
Added routing benchmark
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
69306faf22
|
add a new include netlist for all the fabric-related netlists
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
5c851a8467
|
deploy the fabric/testbench generation only cases to travis
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
a3fe6a9fcb
|
update travis script with example run on MCNC big20
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
9bf91bd92a
|
start testing mcnc_big20 using OpenFPGA tasks
|
2020-06-11 19:30:55 -06:00 |
ganeshgore
|
c31b20dc91
|
Added support for simulation setting file in the task flow
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
49edeb119c
|
BugFix : Relative path for refrence benchmark fixed
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
890ead91b9
|
Fixed modelsim include references
|
2020-06-11 19:28:13 -06:00 |
|
tangxifan
|
8f5a684b10
|
removed redundant include files in all the verilog netlists except the top one
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
c1b73efa62
|
Added support for simulation setting file in the task flow
|
2020-06-10 23:12:30 -06:00 |
|
ganeshgore
|
a3103f6afe
|
BugFix : Relative path for refrence benchmark fixed
|
2020-04-25 20:16:17 -06:00 |
|
ganeshgore
|
9d1b3d6865
|
Fixed modelsim include references
|
2020-04-24 21:53:57 -06:00 |
|
ganeshgore
|
9e46b4eb75
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-24 21:30:51 -06:00 |
|
tangxifan
|
185e574738
|
removed redundant include files in all the verilog netlists except the top one
|
2020-04-24 20:21:32 -06:00 |
|
ganeshgore
|
773790bc2c
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-24 11:00:40 -06:00 |
|
tangxifan
|
e811f8bb21
|
plug in netlist manager and now the include_netlist appears in one unique file
|
2020-04-23 20:42:11 -06:00 |
|
tangxifan
|
87b17fc25f
|
add netlist manager data structure
|
2020-04-23 18:59:09 -06:00 |
|
tangxifan
|
90f608baea
|
changing task mcnc file for debugging (temporarily now) Will be corrected later
|
2020-04-23 18:58:39 -06:00 |
|
tangxifan
|
417d534121
|
fine tune mcnc example script to run Modelsim simulations easily
|
2020-04-23 16:15:45 -06:00 |
|
ganeshgore
|
ca793285ca
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-04-23 12:18:24 -06:00 |
|
tangxifan
|
df85175765
|
fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
|
2020-04-22 21:44:52 -06:00 |
|
tangxifan
|
f9fcc6b471
|
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
|
2020-04-22 18:24:09 -06:00 |
|
tangxifan
|
0c4904065f
|
reduce activity error to warning.
|
2020-04-22 17:36:02 -06:00 |
|
tangxifan
|
bf841b9a8e
|
bug fixed in identifying wired LUT
|
2020-04-22 17:28:16 -06:00 |
|
tangxifan
|
341f38025e
|
add spypad to regression test
|
2020-04-22 14:42:30 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
|
2020-04-22 14:41:16 -06:00 |
|
tangxifan
|
726185cd5e
|
add test cases using spypad architecture
|
2020-04-22 12:56:57 -06:00 |
|
tangxifan
|
73e9006372
|
add arch file with spy pads
|
2020-04-22 12:56:09 -06:00 |
|
tangxifan
|
9fb8971281
|
add FPGA arch with spypads to portofilo
|
2020-04-22 11:12:28 -06:00 |
|
tangxifan
|
9960625b01
|
add example spypad architecture
|
2020-04-22 11:10:59 -06:00 |