3c49af6a08
[test] code format
2024-05-20 21:28:46 -07:00
a9a5fbee34
[test] add fully connected feedback connections to directlist
2024-05-20 17:02:20 -07:00
bdc13e491e
[arch] adding openfpga arch for ecb
2024-05-20 12:04:52 -07:00
65a8db4f38
[arch] replace out-of-date keywords
2024-05-20 11:18:46 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
a4f53c64c6
[test] fixed a bug
2023-09-25 19:28:19 -07:00
663c9c9fa1
[test] add a new test to validate the tile port merge feature
2023-09-25 18:34:34 -07:00
56cedf6c8b
[test] added a new test case to validate the support on different wire segment distribution on X and Y
2023-08-22 11:20:14 -07:00
e4c5265b68
[test] arch syntax
2023-08-18 21:40:56 -07:00
5ac8919ce0
[test] add a new testcase to validate subtile with tile annotations
2023-08-18 21:37:15 -07:00
df771cb33a
[test] add a new testcase for subtile and deploy it to basic regression test
2023-05-03 15:41:29 +08:00
a3f2ae3c33
[arch] format
2023-05-03 15:23:47 +08:00
02a5057449
[arch] add openfpga arch example using subtile; updated documentation
2023-05-03 15:20:49 +08:00
f06248a1b0
[test] add a new testcase to validate the ccff v2
2023-04-24 14:55:22 +08:00
02e964b16f
[test] add a new test case for ccffv2
2023-04-22 15:41:19 +08:00
b242fd97d6
[test] adding new arch and testcase for 2-clock network
2023-04-20 11:31:49 +08:00
780dec6b1b
[test] add a new test to validate the programmable clock arch
2023-02-28 21:46:57 -08:00
e7a3b48475
[arch] comment on the wrong mode bits
2023-01-24 15:24:17 -08:00
fec84d76d1
[arch] adding tech lib;
2023-01-24 15:22:34 -08:00
1d8c1a6803
[arch] adding a new arch to validate fracturable dsp
2023-01-24 15:17:50 -08:00
297092f1fe
[arch] now use a local clock as an input of a CLB
2023-01-14 22:12:00 -08:00
9222d085cd
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
2023-01-13 22:04:56 -08:00
e9ee039e60
Merge branch 'master' into rst_on_lut_strong
2022-10-13 16:01:57 -07:00
33e2b16cb1
[arch] fixed a bug which caused verification failed
2022-10-13 15:33:43 -07:00
1c36ac28f1
[arch] code format
2022-10-13 12:17:32 -07:00
7b7217d116
[arch]add new arch to test
2022-10-13 11:08:51 -07:00
d7a253408d
Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 14:00:59 +03:00
6f55371d4b
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 13:53:32 +03:00
35869b480a
Merge branch 'master' into xmllint
2022-10-07 10:47:43 -07:00
85089cbc88
[arch] apply xml format for all the architecture files
2022-10-07 10:31:51 -07:00
508c01cef6
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-07 09:38:07 +03:00
78f30cf072
[test] add a new test to track the golden netlists where cout is not in GSB
2022-09-30 15:38:27 -07:00
0d8d8446ee
[test] fixed a bug where OPIN for direct connection is included in GSB
2022-09-30 15:24:51 -07:00
b8f1520367
[test] fixed a bug
2022-09-20 18:12:23 -07:00
5e23be19a5
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
2022-09-20 18:07:31 -07:00
7ed1548c6e
[arch] fixed a few bugs
2022-05-09 17:22:48 +08:00
812af4f722
[arch] add arch that supports negative edge triggered flip-flop
2022-05-09 16:32:01 +08:00
c8da85cc24
[Doc] Update naming convention for OpenFPGA architecture files
2022-03-20 10:51:55 +08:00
a1e2d9c864
[Arch] Add a new example openfpga arch where clock ports are independent
2022-03-20 10:50:31 +08:00
9f7a182433
[Arch] Typo
2022-02-24 09:51:26 -08:00
fdaf97e60d
[Test] Update test case by using GPIO with config_done signals
2022-02-24 09:49:34 -08:00
e443a4567d
[Arch] Typo
2022-02-23 22:09:26 -08:00
b27a04eb24
[Test] Now test case has a config done CCFF
2022-02-23 22:07:11 -08:00
62b4a0b7ff
[Flow] Add openfpga arch for DSP with registers
2022-01-02 19:59:33 -08:00
7598455497
[Doc] Update naming convention for architecture files
2022-01-02 19:51:09 -08:00
b8d5920529
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-28 15:45:58 -07:00
2eef21a1af
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
82e77b42c5
[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
2021-10-09 20:43:55 -07:00
d2859ca1c8
[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
2021-10-05 10:56:20 -07:00
fbef22b494
[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
2021-10-04 16:39:53 -07:00
tangxifan
chungshien
mustafa.arslan
Aram Kostanyan