AurelienUoU
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8366f9e7b7
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Update tutorial
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2019-07-08 16:18:08 -06:00 |
Ganesh Gore
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443a73954f
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Removed all local files
+ Removed local configurations and scripts from previous commit
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2019-07-03 14:26:06 -06:00 |
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Ganesh Gore
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57ad71438b
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Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
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2019-07-03 13:39:52 -06:00 |
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Ganesh Gore
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54f6ca2687
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Added lattice benchmark settings
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2019-07-01 11:07:23 -06:00 |
tangxifan
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c54f3905d5
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fixed broken fpga flow
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2019-06-28 13:07:04 -06:00 |
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tangxifan
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0902d1e75a
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c++ string is not working, use char which is stable
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2019-06-13 18:38:46 -06:00 |
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tangxifan
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0f1ed19ad0
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Revert to the use of sprintf instead std::string. Have no idea why string is not working
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2019-06-07 18:54:57 -06:00 |
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AurelienUoU
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a2f6ded2a2
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Add path modification in file changing a keyword into OpenFPGA full path
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2019-06-04 15:21:15 -06:00 |
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AurelienUoU
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ba05a08ef0
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Path correction in tech debugging + correction of yosys rewrite file in fpga_flow
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2019-05-30 09:52:19 -06:00 |
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AurelienUoU
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2b04376209
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Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks
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2019-05-22 13:44:48 -06:00 |
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AurelienUoU
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b4c97f86a3
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Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches
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2019-05-21 17:24:06 -06:00 |
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AurelienUoU
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df8bb0db1a
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Add MCNC Benchmarks netlists generation to travis regression test
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2019-05-17 15:22:04 -06:00 |
Baudouin Chauviere
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79f3db9880
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removed the now useless tutorial part
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2018-12-10 13:57:01 -07:00 |
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Baudouin Chauviere
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d55ecd154b
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Add the PTM to the benchmark flow
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2018-11-21 11:32:34 -07:00 |
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Baudouin Chauviere
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15d69e2bb1
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Generation script finished TODO: integration in flow
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2018-11-20 13:24:31 -07:00 |
Baudouin Chauviere
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9611576d6a
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Update on the examples to respect the new syntax
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2018-11-19 15:50:29 -07:00 |
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Baudouin Chauviere
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dddca8acbb
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Global Makefile and typo correction
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2018-10-24 17:34:51 -06:00 |
Xifan Tang
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158dec405e
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Reorganize the code directory
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2018-07-26 11:28:21 -06:00 |