Ganesh Gore
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4f6b8c0905
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Updated regression tests
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2023-02-11 22:11:06 -07:00 |
tangxifan
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8174f53796
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[test] deploy new test to fpga bitstream regression
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2023-01-24 15:42:01 -08:00 |
tangxifan
|
95dd4fd535
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[test] deploy new test to basic regression tests
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2023-01-18 18:17:53 -08:00 |
tangxifan
|
5aa85d82e6
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[test] deploy the new test to basic regression tests
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2023-01-13 22:07:45 -08:00 |
tangxifan
|
bbf83101be
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[test] deploy new test to ci
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2023-01-11 17:11:28 -08:00 |
tangxifan
|
43cb498827
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[test] deploy new tests to basic regression tests
|
2023-01-01 17:07:25 -08:00 |
tangxifan
|
93b020b0b3
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[test] deploy new test to basic regression tests
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2022-12-30 18:26:22 -08:00 |
tangxifan
|
c33b9f1b9b
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[script] enable eval mode in tcl reg test
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2022-12-02 12:07:27 -08:00 |
tangxifan
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156fac9fec
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[ci] deploy tcl test to ci
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2022-12-02 11:46:14 -08:00 |
tangxifan
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97c72c73f1
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[test] add a small test to validate tcl integration
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2022-12-02 11:43:46 -08:00 |
tangxifan
|
609e096b1a
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[test] added a new test to validate explicit port direction in pin table support
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2022-10-17 15:25:19 -07:00 |
tangxifan
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aa78981e37
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[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
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2022-10-17 11:18:21 -07:00 |
tangxifan
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5cf315958d
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[test] deploy new test to basic regression tests
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2022-10-13 11:17:34 -07:00 |
tangxifan
|
13c819bb28
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[ci] deply new test to ci
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2022-10-01 11:04:08 -07:00 |
tangxifan
|
ce0fbe1765
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[test] fixed a few bugs
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2022-09-29 15:32:31 -07:00 |
tangxifan
|
36603f9772
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Merge branch 'master' into vtr_upgrade
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2022-09-20 21:08:06 -07:00 |
tangxifan
|
e0f632cc9c
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[test] fixed a bug
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2022-09-20 20:29:34 -07:00 |
tangxifan
|
645d8df7b9
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[test] fixed a bug
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2022-09-20 20:09:41 -07:00 |
tangxifan
|
9042fc2422
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[test] now reg test should show diff details when failed
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2022-09-20 19:32:34 -07:00 |
tangxifan
|
da157ed5de
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[test] debugging git-diff
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2022-09-20 15:31:39 -07:00 |
tangxifan
|
6a896a9845
|
[test] debugging
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2022-09-20 14:08:22 -07:00 |
tangxifan
|
ecfdc4a83a
|
[test] debugging
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2022-09-20 13:51:32 -07:00 |
tangxifan
|
bdcdc7d294
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[test] Now git diff in basic regression tests should capture the changes on golden outputs
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2022-09-20 13:36:31 -07:00 |
tangxifan
|
373566416c
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
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2022-09-16 16:47:21 -07:00 |
tangxifan
|
a2e22787c2
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[test] deploy the new test cases to the basic regression tests
|
2022-09-16 10:31:15 -07:00 |
tangxifan
|
91fe27ff66
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[test] deploy new test to ci
|
2022-09-09 17:00:28 -07:00 |
tangxifan
|
95d7a17b3c
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Merge branch 'master' into vtr_upgrade
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2022-09-09 14:32:42 -07:00 |
tangxifan
|
a840aeea7a
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[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
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2022-09-08 16:27:11 -07:00 |
tangxifan
|
56619f9a47
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
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2022-09-06 14:59:00 -07:00 |
tangxifan
|
9e1abf5898
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Merge branch 'master' into vtr_upgrade
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2022-09-01 21:39:14 -07:00 |
tangxifan
|
c48f750f86
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[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
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2022-09-01 20:10:29 -07:00 |
tangxifan
|
71ad0721a1
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Merge branch 'master' into vtr_upgrade
|
2022-08-31 13:56:17 -07:00 |
tangxifan
|
201bca8968
|
[test] typo
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2022-08-30 08:59:20 -07:00 |
tangxifan
|
5f88b9a226
|
[test] typo
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2022-08-29 22:41:15 -07:00 |
tangxifan
|
0b5bdcdbb1
|
[test] deploy new test to basic regression tests
|
2022-08-29 22:07:56 -07:00 |
tangxifan
|
8d6682c28b
|
[test] fixed a bug when removing previous runs
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2022-08-25 16:20:18 -07:00 |
tangxifan
|
6ce1d4804c
|
[test] deploy new test case to basic regression tests
|
2022-08-01 21:05:05 -07:00 |
taoli4rs
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347a29f27c
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Fix test name in basic regression test script.
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2022-07-20 21:05:31 -07:00 |
taoli4rs
|
cfc0d08060
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Add constrain_pin_location command in openfpga; add full flow test.
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2022-07-20 11:51:00 -07:00 |
tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
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2022-05-25 11:42:32 +08:00 |
tangxifan
|
86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |
tangxifan
|
7d694acf32
|
[test] debugging basic reg test paths
|
2022-05-23 11:21:36 +08:00 |
tangxifan
|
b41cbad5d3
|
[test] force to run git diff under root directory
|
2022-05-23 10:32:43 +08:00 |
tangxifan
|
488a934097
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[test] give abs path for git diff in basic regression tests
|
2022-05-23 09:12:33 +08:00 |
tangxifan
|
0dc7caf3b7
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[test] now regression test script supports remove all run dir through command-line options
|
2022-05-22 13:15:39 +08:00 |
tangxifan
|
751d87b8e3
|
[test] fix a bug in detect changes in golden netlists
|
2022-05-22 13:06:47 +08:00 |
tangxifan
|
d7e854eae7
|
[test] deploy new test to ci
|
2022-05-09 17:23:57 +08:00 |
Ganesh Gore
|
522982c9ba
|
Adde vtr_benchmarks_template for demo
|
2022-05-06 22:40:36 -06:00 |
Ganesh Gore
|
1e243650b9
|
Added option to copy example projects
|
2022-05-03 14:06:16 -06:00 |