tangxifan
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7d0c23c675
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[lib] new api for lowest level clock connections
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2023-02-27 15:16:23 -08:00 |
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tangxifan
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b3dec93eb9
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[core] code format
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2023-02-27 15:12:59 -08:00 |
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tangxifan
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9ec4d690db
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[core] clock edges interconnecting clock tracks across levels
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2023-02-27 15:10:36 -08:00 |
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tangxifan
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b6eace8fac
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[core] now switch id is linked in clock network
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2023-02-27 13:10:54 -08:00 |
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tangxifan
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009d711ba5
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[core] code format
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2023-02-26 22:23:41 -08:00 |
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tangxifan
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87a9146082
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[core] adding rr spatial lookup for clock nodes only
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2023-02-26 22:23:17 -08:00 |
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tangxifan
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db36f87dfa
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[core] enhance clock tree arch validation
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2023-02-26 18:39:53 -08:00 |
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tangxifan
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780fc0f26d
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[core] developing validators and annotate rr_segment for clock arch
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2023-02-26 18:03:55 -08:00 |
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tangxifan
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75773ddd4e
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[code] format
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2023-02-26 12:46:29 -08:00 |
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tangxifan
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3db5acfb37
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[core] dev
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2023-02-26 12:40:13 -08:00 |
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tangxifan
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8f0d94ba73
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[code] format
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2023-02-25 22:43:21 -08:00 |
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tangxifan
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0b33650761
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[core] dev
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2023-02-25 22:41:33 -08:00 |
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tangxifan
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7f07a9d031
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[lib] add default seg/switch to clock arch. Fixed syntax
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2023-02-24 19:15:39 -08:00 |
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tangxifan
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65b27a3377
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[lib] fixed a few bugs
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2023-02-22 21:29:18 -08:00 |
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tangxifan
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40f6b5a3fe
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[lib] fixed a few bugs
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2023-02-22 21:23:08 -08:00 |
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tangxifan
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a9d5e4dfbd
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[lib] update example clock arch xml
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2023-02-22 21:18:00 -08:00 |
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tangxifan
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d1133000ba
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[lib] code format
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2023-02-22 21:03:04 -08:00 |
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tangxifan
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aafd1e6fb3
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[lib] syntax
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2023-02-22 21:02:35 -08:00 |
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tangxifan
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b2ef1db5f4
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[lib] finishing up code changes; start debugging
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2023-02-22 20:46:18 -08:00 |
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tangxifan
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1c8a5eb098
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[lib] adding linker
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2023-02-22 20:29:32 -08:00 |
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tangxifan
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bf2876c60e
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[lib] developing linker
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2023-02-22 18:36:22 -08:00 |
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tangxifan
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ce20a16aad
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[lib] adding unit test
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2023-02-22 18:26:18 -08:00 |
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tangxifan
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b37deb4b02
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[lib] adding writer
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2023-02-22 18:21:28 -08:00 |
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tangxifan
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5cd310c4cc
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[lib] adding missing apis
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2023-02-22 15:04:52 -08:00 |
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tangxifan
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7bc843b74a
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[lib] developing xml parser for clk arch
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2023-02-22 13:23:09 -08:00 |
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tangxifan
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25e43b47da
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[lib] first round of data structure on clock arch
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2023-02-22 12:18:44 -08:00 |
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tangxifan
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9eb2374bc6
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[lib] developing
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2023-02-21 22:29:25 -08:00 |
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tangxifan
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fe594acab1
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[lib] adding clock network data structure
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2023-02-21 16:53:05 -08:00 |
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tangxifan
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e7fc065032
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[lib] start developing clock arch data structure and I/O
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2023-02-21 15:06:35 -08:00 |